📄 cpu.h.svn-base
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void cpu_loop_exit (void);void dump_stack (CPUPPCState *env);#if !defined(CONFIG_USER_ONLY)target_ulong do_load_ibatu (CPUPPCState *env, int nr);target_ulong do_load_ibatl (CPUPPCState *env, int nr);void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);target_ulong do_load_dbatu (CPUPPCState *env, int nr);target_ulong do_load_dbatl (CPUPPCState *env, int nr);void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);target_ulong do_load_sdr1 (CPUPPCState *env);void do_store_sdr1 (CPUPPCState *env, target_ulong value);#if defined(TARGET_PPC64)target_ulong ppc_load_asr (CPUPPCState *env);void ppc_store_asr (CPUPPCState *env, target_ulong value);target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);#endif /* defined(TARGET_PPC64) */#if 0 // Unusedtarget_ulong do_load_sr (CPUPPCState *env, int srnum);#endifvoid do_store_sr (CPUPPCState *env, int srnum, target_ulong value);#endif /* !defined(CONFIG_USER_ONLY) */target_ulong ppc_load_xer (CPUPPCState *env);void ppc_store_xer (CPUPPCState *env, target_ulong value);void ppc_store_msr (CPUPPCState *env, target_ulong value);void cpu_ppc_reset (void *opaque);void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);/* Time-base and decrementer management */#ifndef NO_CPU_IO_DEFSuint32_t cpu_ppc_load_tbl (CPUPPCState *env);uint32_t cpu_ppc_load_tbu (CPUPPCState *env);void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);uint32_t cpu_ppc_load_atbl (CPUPPCState *env);uint32_t cpu_ppc_load_atbu (CPUPPCState *env);void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);uint32_t cpu_ppc_load_decr (CPUPPCState *env);void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);uint64_t cpu_ppc_load_purr (CPUPPCState *env);void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);#if !defined(CONFIG_USER_ONLY)void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);target_ulong load_40x_pit (CPUPPCState *env);void store_40x_pit (CPUPPCState *env, target_ulong val);void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);void store_40x_sler (CPUPPCState *env, uint32_t val);void store_booke_tcr (CPUPPCState *env, target_ulong val);void store_booke_tsr (CPUPPCState *env, target_ulong val);void ppc_tlb_invalidate_all (CPUPPCState *env);void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);#if defined(TARGET_PPC64)void ppc_slb_invalidate_all (CPUPPCState *env);void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);#endifint ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);#endif#endifstatic always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn){ uint64_t gprv; gprv = env->gpr[gprn];#if !defined(TARGET_PPC64) if (env->flags & POWERPC_FLAG_SPE) { /* If the CPU implements the SPE extension, we have to get the * high bits of the GPR from the gprh storage area */ gprv &= 0xFFFFFFFFULL; gprv |= (uint64_t)env->gprh[gprn] << 32; }#endif return gprv;}/* Device control registers */int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);#define CPUState CPUPPCState#define cpu_init cpu_ppc_init#define cpu_exec cpu_ppc_exec#define cpu_gen_code cpu_ppc_gen_code#define cpu_signal_handler cpu_ppc_signal_handler#define cpu_list ppc_cpu_list/* MMU modes definitions */#define MMU_MODE0_SUFFIX _user#define MMU_MODE1_SUFFIX _kernel#define MMU_MODE2_SUFFIX _hypv#define MMU_USER_IDX 0static inline int cpu_mmu_index (CPUState *env){ return env->mmu_idx;}#include "cpu-all.h"/*****************************************************************************//* Registers definitions */#define XER_SO 31#define XER_OV 30#define XER_CA 29#define XER_CMP 8#define XER_BC 0#define xer_so env->xer[4]#define xer_ov env->xer[6]#define xer_ca env->xer[2]#define xer_cmp env->xer[1]#define xer_bc env->xer[0]/* SPR definitions */#define SPR_MQ (0x000)#define SPR_XER (0x001)#define SPR_601_VRTCU (0x004)#define SPR_601_VRTCL (0x005)#define SPR_601_UDECR (0x006)#define SPR_LR (0x008)#define SPR_CTR (0x009)#define SPR_DSISR (0x012)#define SPR_DAR (0x013) /* DAE for PowerPC 601 */#define SPR_601_RTCU (0x014)#define SPR_601_RTCL (0x015)#define SPR_DECR (0x016)#define SPR_SDR1 (0x019)#define SPR_SRR0 (0x01A)#define SPR_SRR1 (0x01B)#define SPR_AMR (0x01D)#define SPR_BOOKE_PID (0x030)#define SPR_BOOKE_DECAR (0x036)#define SPR_BOOKE_CSRR0 (0x03A)#define SPR_BOOKE_CSRR1 (0x03B)#define SPR_BOOKE_DEAR (0x03D)#define SPR_BOOKE_ESR (0x03E)#define SPR_BOOKE_IVPR (0x03F)#define SPR_MPC_EIE (0x050)#define SPR_MPC_EID (0x051)#define SPR_MPC_NRI (0x052)#define SPR_CTRL (0x088)#define SPR_MPC_CMPA (0x090)#define SPR_MPC_CMPB (0x091)#define SPR_MPC_CMPC (0x092)#define SPR_MPC_CMPD (0x093)#define SPR_MPC_ECR (0x094)#define SPR_MPC_DER (0x095)#define SPR_MPC_COUNTA (0x096)#define SPR_MPC_COUNTB (0x097)#define SPR_UCTRL (0x098)#define SPR_MPC_CMPE (0x098)#define SPR_MPC_CMPF (0x099)#define SPR_MPC_CMPG (0x09A)#define SPR_MPC_CMPH (0x09B)#define SPR_MPC_LCTRL1 (0x09C)#define SPR_MPC_LCTRL2 (0x09D)#define SPR_MPC_ICTRL (0x09E)#define SPR_MPC_BAR (0x09F)#define SPR_VRSAVE (0x100)#define SPR_USPRG0 (0x100)#define SPR_USPRG1 (0x101)#define SPR_USPRG2 (0x102)#define SPR_USPRG3 (0x103)#define SPR_USPRG4 (0x104)#define SPR_USPRG5 (0x105)#define SPR_USPRG6 (0x106)#define SPR_USPRG7 (0x107)#define SPR_VTBL (0x10C)#define SPR_VTBU (0x10D)#define SPR_SPRG0 (0x110)#define SPR_SPRG1 (0x111)#define SPR_SPRG2 (0x112)#define SPR_SPRG3 (0x113)#define SPR_SPRG4 (0x114)#define SPR_SCOMC (0x114)#define SPR_SPRG5 (0x115)#define SPR_SCOMD (0x115)#define SPR_SPRG6 (0x116)#define SPR_SPRG7 (0x117)#define SPR_ASR (0x118)#define SPR_EAR (0x11A)#define SPR_TBL (0x11C)#define SPR_TBU (0x11D)#define SPR_TBU40 (0x11E)#define SPR_SVR (0x11E)#define SPR_BOOKE_PIR (0x11E)#define SPR_PVR (0x11F)#define SPR_HSPRG0 (0x130)#define SPR_BOOKE_DBSR (0x130)#define SPR_HSPRG1 (0x131)#define SPR_HDSISR (0x132)#define SPR_HDAR (0x133)#define SPR_BOOKE_DBCR0 (0x134)#define SPR_IBCR (0x135)#define SPR_PURR (0x135)#define SPR_BOOKE_DBCR1 (0x135)#define SPR_DBCR (0x136)#define SPR_HDEC (0x136)#define SPR_BOOKE_DBCR2 (0x136)#define SPR_HIOR (0x137)#define SPR_MBAR (0x137)#define SPR_RMOR (0x138)#define SPR_BOOKE_IAC1 (0x138)#define SPR_HRMOR (0x139)#define SPR_BOOKE_IAC2 (0x139)#define SPR_HSRR0 (0x13A)#define SPR_BOOKE_IAC3 (0x13A)#define SPR_HSRR1 (0x13B)#define SPR_BOOKE_IAC4 (0x13B)#define SPR_LPCR (0x13C)#define SPR_BOOKE_DAC1 (0x13C)#define SPR_LPIDR (0x13D)#define SPR_DABR2 (0x13D)#define SPR_BOOKE_DAC2 (0x13D)#define SPR_BOOKE_DVC1 (0x13E)#define SPR_BOOKE_DVC2 (0x13F)#define SPR_BOOKE_TSR (0x150)#define SPR_BOOKE_TCR (0x154)#define SPR_BOOKE_IVOR0 (0x190)#define SPR_BOOKE_IVOR1 (0x191)#define SPR_BOOKE_IVOR2 (0x192)#define SPR_BOOKE_IVOR3 (0x193)#define SPR_BOOKE_IVOR4 (0x194)#define SPR_BOOKE_IVOR5 (0x195)#define SPR_BOOKE_IVOR6 (0x196)#define SPR_BOOKE_IVOR7 (0x197)#define SPR_BOOKE_IVOR8 (0x198)#define SPR_BOOKE_IVOR9 (0x199)#define SPR_BOOKE_IVOR10 (0x19A)#define SPR_BOOKE_IVOR11 (0x19B)#define SPR_BOOKE_IVOR12 (0x19C)#define SPR_BOOKE_IVOR13 (0x19D)#define SPR_BOOKE_IVOR14 (0x19E)#define SPR_BOOKE_IVOR15 (0x19F)#define SPR_BOOKE_SPEFSCR (0x200)#define SPR_Exxx_BBEAR (0x201)#define SPR_Exxx_BBTAR (0x202)#define SPR_Exxx_L1CFG0 (0x203)#define SPR_Exxx_NPIDR (0x205)#define SPR_ATBL (0x20E)#define SPR_ATBU (0x20F)#define SPR_IBAT0U (0x210)#define SPR_BOOKE_IVOR32 (0x210)#define SPR_RCPU_MI_GRA (0x210)#define SPR_IBAT0L (0x211)#define SPR_BOOKE_IVOR33 (0x211)#define SPR_IBAT1U (0x212)#define SPR_BOOKE_IVOR34 (0x212)#define SPR_IBAT1L (0x213)#define SPR_BOOKE_IVOR35 (0x213)#define SPR_IBAT2U (0x214)#define SPR_BOOKE_IVOR36 (0x214)#define SPR_IBAT2L (0x215)#define SPR_BOOKE_IVOR37 (0x215)#define SPR_IBAT3U (0x216)#define SPR_IBAT3L (0x217)#define SPR_DBAT0U (0x218)#define SPR_RCPU_L2U_GRA (0x218)#define SPR_DBAT0L (0x219)#define SPR_DBAT1U (0x21A)#define SPR_DBAT1L (0x21B)#define SPR_DBAT2U (0x21C)#define SPR_DBAT2L (0x21D)#define SPR_DBAT3U (0x21E)#define SPR_DBAT3L (0x21F)#define SPR_IBAT4U (0x230)#define SPR_RPCU_BBCMCR (0x230)#define SPR_MPC_IC_CST (0x230)#define SPR_Exxx_CTXCR (0x230)#define SPR_IBAT4L (0x231)#define SPR_MPC_IC_ADR (0x231)#define SPR_Exxx_DBCR3 (0x231)#define SPR_IBAT5U (0x232)#define SPR_MPC_IC_DAT (0x232)#define SPR_Exxx_DBCNT (0x232)#define SPR_IBAT5L (0x233)#define SPR_IBAT6U (0x234)#define SPR_IBAT6L (0x235)#define SPR_IBAT7U (0x236)#define SPR_IBAT7L (0x237)#define SPR_DBAT4U (0x238)#define SPR_RCPU_L2U_MCR (0x238)#define SPR_MPC_DC_CST (0x238)#define SPR_Exxx_ALTCTXCR (0x238)#define SPR_DBAT4L (0x239)#define SPR_MPC_DC_ADR (0x239)#define SPR_DBAT5U (0x23A)#define SPR_BOOKE_MCSRR0 (0x23A)#define SPR_MPC_DC_DAT (0x23A)#define SPR_DBAT5L (0x23B)#define SPR_BOOKE_MCSRR1 (0x23B)#define SPR_DBAT6U (0x23C)#define SPR_BOOKE_MCSR (0x23C)#define SPR_DBAT6L (0x23D)#define SPR_Exxx_MCAR (0x23D)#define SPR_DBAT7U (0x23E)#define SPR_BOOKE_DSRR0 (0x23E)#define SPR_DBAT7L (0x23F)#define SPR_BOOKE_DSRR1 (0x23F)#define SPR_BOOKE_SPRG8 (0x25C)#define SPR_BOOKE_SPRG9 (0x25D)#define SPR_BOOKE_MAS0 (0x270)#define SPR_BOOKE_MAS1 (0x271)#define SPR_BOOKE_MAS2 (0x272)#define SPR_BOOKE_MAS3 (0x273)#define SPR_BOOKE_MAS4 (0x274)#define SPR_BOOKE_MAS5 (0x275)#define SPR_BOOKE_MAS6 (0x276)#define SPR_BOOKE_PID1 (0x279)#define SPR_BOOKE_PID2 (0x27A)#define SPR_MPC_DPDR (0x280)//#define SPR_MPC_IMMR (0x288) debugger#define SPR_MPC_IMMR (0x27E)//debugger#define SPR_BOOKE_TLB0CFG (0x2B0)#define SPR_BOOKE_TLB1CFG (0x2B1)#define SPR_BOOKE_TLB2CFG (0x2B2)#define SPR_BOOKE_TLB3CFG (0x2B3)#define SPR_BOOKE_EPR (0x2BE)#define SPR_PERF0 (0x300)#define SPR_RCPU_MI_RBA0 (0x300)#define SPR_MPC_MI_CTR (0x300)#define SPR_PERF1 (0x301)#define SPR_RCPU_MI_RBA1 (0x301)#define SPR_PERF2 (0x302)#define SPR_RCPU_MI_RBA2 (0x302)#define SPR_MPC_MI_AP (0x302)#define SPR_PERF3 (0x303)#define SPR_620_PMC1R (0x303)#define SPR_RCPU_MI_RBA3 (0x303)#define SPR_MPC_MI_EPN (0x303)#define SPR_PERF4 (0x304)#define SPR_620_PMC2R (0x304)#define SPR_PERF5 (0x305)#define SPR_MPC_MI_TWC (0x305)#define SPR_PERF6 (0x306)#define SPR_MPC_MI_RPN (0x306)#define SPR_PERF7 (0x307)#define SPR_PERF8 (0x308)#define SPR_RCPU_L2U_RBA0 (0x308)⌨️ 快捷键说明
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