vmware_vga.c.svn-base

我们自己开发的一个OSEK操作系统！不知道可不可以？

    case SVGA_REG_CURSOR_X:
        s->cursor.x = value;
        break;

    case SVGA_REG_CURSOR_Y:
        s->cursor.y = value;
        break;

    case SVGA_REG_CURSOR_ON:
        s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
        s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
#ifdef HW_MOUSE_ACCEL
        if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
            s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
#endif
        break;

    case SVGA_REG_MEM_REGS:
    case SVGA_REG_NUM_DISPLAYS:
    case SVGA_REG_PITCHLOCK:
    case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
        break;

    default:
        if (s->index >= SVGA_SCRATCH_BASE &&
                s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
            s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
            break;
        }
        printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
    }
}

static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
{
    printf("%s: what are we supposed to return?\n", __FUNCTION__);
    return 0xcafe;
}

static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
{
    printf("%s: what are we supposed to do with (%08x)?\n",
                    __FUNCTION__, data);
}

static inline void vmsvga_size(struct vmsvga_state_s *s)
{
    if (s->new_width != s->width || s->new_height != s->height) {
        s->width = s->new_width;
        s->height = s->new_height;
        dpy_resize(s->ds, s->width, s->height);
        s->invalidated = 1;
    }
}

static void vmsvga_update_display(void *opaque)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    if (!s->enable) {
#ifdef EMBED_STDVGA
        s->update(opaque);
#endif
        return;
    }

    vmsvga_size(s);

    vmsvga_fifo_run(s);
    vmsvga_update_rect_flush(s);

    /*
     * Is it more efficient to look at vram VGA-dirty bits or wait
     * for the driver to issue SVGA_CMD_UPDATE?
     */
    if (s->invalidated) {
        s->invalidated = 0;
        vmsvga_update_screen(s);
    }
}

static void vmsvga_reset(struct vmsvga_state_s *s)
{
    s->index = 0;
    s->enable = 0;
    s->config = 0;
    s->width = -1;
    s->height = -1;
    s->svgaid = SVGA_ID;
    s->depth = s->ds->depth ? s->ds->depth : 24;
    s->bypp = (s->depth + 7) >> 3;
    s->cursor.on = 0;
    s->redraw_fifo_first = 0;
    s->redraw_fifo_last = 0;
    switch (s->depth) {
    case 8:
        s->wred   = 0x00000007;
        s->wgreen = 0x00000038;
        s->wblue  = 0x000000c0;
        break;
    case 15:
        s->wred   = 0x0000001f;
        s->wgreen = 0x000003e0;
        s->wblue  = 0x00007c00;
        break;
    case 16:
        s->wred   = 0x0000001f;
        s->wgreen = 0x000007e0;
        s->wblue  = 0x0000f800;
        break;
    case 24:
        s->wred   = 0x00ff0000;
        s->wgreen = 0x0000ff00;
        s->wblue  = 0x000000ff;
        break;
    case 32:
        s->wred   = 0x00ff0000;
        s->wgreen = 0x0000ff00;
        s->wblue  = 0x000000ff;
        break;
    }
    s->syncing = 0;
}

static void vmsvga_invalidate_display(void *opaque)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    if (!s->enable) {
#ifdef EMBED_STDVGA
        s->invalidate(opaque);
#endif
        return;
    }

    s->invalidated = 1;
}

/* save the vga display in a PPM image even if no display is
   available */
static void vmsvga_screen_dump(void *opaque, const char *filename)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    if (!s->enable) {
#ifdef EMBED_STDVGA
        s->screen_dump(opaque, filename);
#endif
        return;
    }

    if (s->depth == 32) {
        ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
    }
}

#ifdef DIRECT_VRAM
static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    addr -= SVGA_MEM_BASE;
    if (addr < s->fb_size)
        return *(uint8_t *) (s->ds->data + addr);
    else
        return *(uint8_t *) (s->vram + addr);
}

static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    addr -= SVGA_MEM_BASE;
    if (addr < s->fb_size)
        return *(uint16_t *) (s->ds->data + addr);
    else
        return *(uint16_t *) (s->vram + addr);
}

static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    addr -= SVGA_MEM_BASE;
    if (addr < s->fb_size)
        return *(uint32_t *) (s->ds->data + addr);
    else
        return *(uint32_t *) (s->vram + addr);
}

static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
                uint32_t value)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    addr -= SVGA_MEM_BASE;
    if (addr < s->fb_size)
        *(uint8_t *) (s->ds->data + addr) = value;
    else
        *(uint8_t *) (s->vram + addr) = value;
}

static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
                uint32_t value)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    addr -= SVGA_MEM_BASE;
    if (addr < s->fb_size)
        *(uint16_t *) (s->ds->data + addr) = value;
    else
        *(uint16_t *) (s->vram + addr) = value;
}

static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
                uint32_t value)
{
    struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
    addr -= SVGA_MEM_BASE;
    if (addr < s->fb_size)
        *(uint32_t *) (s->ds->data + addr) = value;
    else
        *(uint32_t *) (s->vram + addr) = value;
}

static CPUReadMemoryFunc *vmsvga_vram_read[] = {
    vmsvga_vram_readb,
    vmsvga_vram_readw,
    vmsvga_vram_readl,
};

static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
    vmsvga_vram_writeb,
    vmsvga_vram_writew,
    vmsvga_vram_writel,
};
#endif

static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
{
    qemu_put_be32(f, s->depth);
    qemu_put_be32(f, s->enable);
    qemu_put_be32(f, s->config);
    qemu_put_be32(f, s->cursor.id);
    qemu_put_be32(f, s->cursor.x);
    qemu_put_be32(f, s->cursor.y);
    qemu_put_be32(f, s->cursor.on);
    qemu_put_be32(f, s->index);
    qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
    qemu_put_be32(f, s->new_width);
    qemu_put_be32(f, s->new_height);
    qemu_put_be32s(f, &s->guest);
    qemu_put_be32s(f, &s->svgaid);
    qemu_put_be32(f, s->syncing);
    qemu_put_be32(f, s->fb_size);
}

static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
{
    int depth;
    depth=qemu_get_be32(f);
    s->enable=qemu_get_be32(f);
    s->config=qemu_get_be32(f);
    s->cursor.id=qemu_get_be32(f);
    s->cursor.x=qemu_get_be32(f);
    s->cursor.y=qemu_get_be32(f);
    s->cursor.on=qemu_get_be32(f);
    s->index=qemu_get_be32(f);
    qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
    s->new_width=qemu_get_be32(f);
    s->new_height=qemu_get_be32(f);
    qemu_get_be32s(f, &s->guest);
    qemu_get_be32s(f, &s->svgaid);
    s->syncing=qemu_get_be32(f);
    s->fb_size=qemu_get_be32(f);

    if (s->enable && depth != s->depth) {
        printf("%s: need colour depth of %i bits to resume operation.\n",
                        __FUNCTION__, depth);
        return -EINVAL;
    }

    s->invalidated = 1;
    if (s->config)
        s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];

    return 0;
}

static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
                uint8_t *vga_ram_base, unsigned long vga_ram_offset,
                int vga_ram_size)
{
    int iomemtype;
    s->ds = ds;
    s->vram = vga_ram_base;
    s->vram_size = vga_ram_size;

    s->scratch_size = SVGA_SCRATCH_SIZE;
    s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);

    vmsvga_reset(s);

#ifdef DIRECT_VRAM
    iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
                    vmsvga_vram_write, s);
#else
    iomemtype = vga_ram_offset | IO_MEM_RAM;
#endif
    cpu_register_physical_memory(SVGA_MEM_BASE, vga_ram_size,
                    iomemtype);

    register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_INDEX_PORT,
                    1, 4, vmsvga_index_read, s);
    register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_INDEX_PORT,
                    1, 4, vmsvga_index_write, s);
    register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_VALUE_PORT,
                    1, 4, vmsvga_value_read, s);
    register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_VALUE_PORT,
                    1, 4, vmsvga_value_write, s);
    register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_BIOS_PORT,
                    1, 4, vmsvga_bios_read, s);
    register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_BIOS_PORT,
                    1, 4, vmsvga_bios_write, s);

    graphic_console_init(ds, vmsvga_update_display,
                    vmsvga_invalidate_display, vmsvga_screen_dump, s);

#ifdef EMBED_STDVGA
    vga_common_init((VGAState *) s, ds,
                    vga_ram_base, vga_ram_offset, vga_ram_size);
    vga_init((VGAState *) s);
#endif
}

static void pci_vmsvga_save(QEMUFile *f, void *opaque)
{
    struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
    pci_device_save(&s->card, f);
    vmsvga_save(&s->chip, f);
}

static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
{
    struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
    int ret;

    ret = pci_device_load(&s->card, f);
    if (ret < 0)
        return ret;

    ret = vmsvga_load(&s->chip, f);
    if (ret < 0)
        return ret;

    return 0;
}

#define PCI_VENDOR_ID_VMWARE		0x15ad
#define PCI_DEVICE_ID_VMWARE_SVGA2	0x0405
#define PCI_DEVICE_ID_VMWARE_SVGA	0x0710
#define PCI_DEVICE_ID_VMWARE_NET	0x0720
#define PCI_DEVICE_ID_VMWARE_SCSI	0x0730
#define PCI_DEVICE_ID_VMWARE_IDE	0x1729
#define PCI_CLASS_BASE_DISPLAY		0x03
#define PCI_CLASS_SUB_VGA		0x00
#define PCI_CLASS_HEADERTYPE_00h	0x00

void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                     unsigned long vga_ram_offset, int vga_ram_size)
{
    struct pci_vmsvga_state_s *s;

    /* Setup PCI configuration */
    s = (struct pci_vmsvga_state_s *)
        pci_register_device(bus, "QEMUware SVGA",
                sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
    s->card.config[PCI_VENDOR_ID]	= PCI_VENDOR_ID_VMWARE & 0xff;
    s->card.config[PCI_VENDOR_ID + 1]	= PCI_VENDOR_ID_VMWARE >> 8;
    s->card.config[PCI_DEVICE_ID]	= SVGA_PCI_DEVICE_ID & 0xff;
    s->card.config[PCI_DEVICE_ID + 1]	= SVGA_PCI_DEVICE_ID >> 8;
    s->card.config[PCI_COMMAND]		= 0x07;		/* I/O + Memory */
    s->card.config[PCI_CLASS_DEVICE]	= PCI_CLASS_SUB_VGA;
    s->card.config[0x0b]		= PCI_CLASS_BASE_DISPLAY;
    s->card.config[0x0c]		= 0x08;		/* Cache line size */
    s->card.config[0x0d]		= 0x40;		/* Latency timer */
    s->card.config[0x0e]		= PCI_CLASS_HEADERTYPE_00h;
    s->card.config[0x10]		= ((SVGA_IO_BASE >>  0) & 0xff) | 1;
    s->card.config[0x11]		=  (SVGA_IO_BASE >>  8) & 0xff;
    s->card.config[0x12]		=  (SVGA_IO_BASE >> 16) & 0xff;
    s->card.config[0x13]		=  (SVGA_IO_BASE >> 24) & 0xff;
    s->card.config[0x18]		= (SVGA_MEM_BASE >>  0) & 0xff;
    s->card.config[0x19]		= (SVGA_MEM_BASE >>  8) & 0xff;
    s->card.config[0x1a]		= (SVGA_MEM_BASE >> 16) & 0xff;
    s->card.config[0x1b]		= (SVGA_MEM_BASE >> 24) & 0xff;
    s->card.config[0x2c]		= PCI_VENDOR_ID_VMWARE & 0xff;
    s->card.config[0x2d]		= PCI_VENDOR_ID_VMWARE >> 8;
    s->card.config[0x2e]		= SVGA_PCI_DEVICE_ID & 0xff;
    s->card.config[0x2f]		= SVGA_PCI_DEVICE_ID >> 8;
    s->card.config[0x3c]		= 0xff;		/* End */

    vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
}