📄 count_16.v
字号:
module count_16 (clk, reset, enable, q);
input clk, reset, enable;
output [15:0] q;
reg [15:0] q;
//在四个数码管上分别显示时分秒,最低秒位计满9时进1,次低位计满5时进1;当秒位计满59秒时进1,分位开始计数
//四个数码管显示分秒分别对应16位计数器的计数值(每4位一组)
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
q <= 0;
else
begin
if (enable) //同步使能
q <= q + 1;
if (q[3:0] == 4'h9)
begin
q[3:0] <= 4'h0;
q[7:4] <= q[7:4] + 1;
end
if ((q[3:0] == 4'h9) && (q[7:4] == 4'h5))
begin
q[7:4] <= 4'h0;
q[3:0] <= 4'h0;
q[11:8] <= q[11:8] + 1;
end
if ((q[3:0] == 4'h9) && (q[7:4] == 4'h5) && (q[11:8] == 4'h9))
begin
q[11:8] <= 4'h0;
q[7:4] <= 4'h0;
q[3:0] <= 4'h0;
q[15:12] <= q[15:12] + 1;
end
if ((q[3:0] == 4'h9) && (q[7:4] == 4'h5)
&& (q[11:8] == 4'h9) && (q[15:12] == 4'h5))
q[15:12] <= 4'h0;
end
end
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -