de2_tv.fit.smsg

DE2_TV_m_write.rar是用来去处抖动的

        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 38 total pin(s) used --  26 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 7 total pin(s) used --  56 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  44 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  54 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  63 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  56 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  58 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  56 pins available
Warning: Ignored I/O standard assignments to the following nodes
    Warning: Ignored I/O standard assignment to node "AUD_ADCDAT"
    Warning: Ignored I/O standard assignment to node "AUD_ADCLRCK"
    Warning: Ignored I/O standard assignment to node "AUD_BCLK"
    Warning: Ignored I/O standard assignment to node "AUD_DACDAT"
    Warning: Ignored I/O standard assignment to node "AUD_DACLRCK"
    Warning: Ignored I/O standard assignment to node "AUD_XCK"
    Warning: Ignored I/O standard assignment to node "ENET_DATA[0]"
    Warning: Ignored I/O standard assignment to node "FL_ADDR[20]"
    Warning: Ignored I/O standard assignment to node "FL_ADDR[21]"
    Warning: Ignored I/O standard assignment to node "SD_DAT3"
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
    Warning: Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
    Warning: Node "I2C_SCLK" is assigned to location or region, but does not exist in design
    Warning: Node "I2C_SDAT" is assigned to location or region, but does not exist in design
    Warning: Node "reset_n" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:22
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:03:09
Info: Estimated most critical path is register to register delay of 16.921 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y11; Fanout = 2; REG Node = 'avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|fifo_contains_ones_n'
    Info: 2: + IC(1.374 ns) + CELL(0.206 ns) = 1.580 ns; Loc. = LAB_X21_Y11; Fanout = 1; COMB Node = 'avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~197'
    Info: 3: + IC(0.494 ns) + CELL(0.624 ns) = 2.698 ns; Loc. = LAB_X22_Y11; Fanout = 1; COMB Node = 'avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198'
    Info: 4: + IC(0.859 ns) + CELL(0.651 ns) = 4.208 ns; Loc. = LAB_X20_Y11; Fanout = 6; COMB Node = 'avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1'
    Info: 5: + IC(0.606 ns) + CELL(0.596 ns) = 5.410 ns; Loc. = LAB_X20_Y11; Fanout = 2; COMB Node = 'avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126'
    Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 5.916 ns; Loc. = LAB_X20_Y11; Fanout = 2; COMB Node = 'avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~127'
    Info: 7: + IC(0.442 ns) + CELL(0.370 ns) = 6.728 ns; Loc. = LAB_X20_Y11; Fanout = 10; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|rdreq~34'
    Info: 8: + IC(0.188 ns) + CELL(0.624 ns) = 7.540 ns; Loc. = LAB_X20_Y11; Fanout = 58; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|Selector0~23'
    Info: 9: + IC(2.838 ns) + CELL(0.202 ns) = 10.580 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address~683'
    Info: 10: + IC(0.579 ns) + CELL(0.621 ns) = 11.780 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|Add1~900'
    Info: 11: + IC(0.000 ns) + CELL(0.506 ns) = 12.286 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|Add1~901'
    Info: 12: + IC(0.885 ns) + CELL(0.621 ns) = 13.792 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[2]~685'
    Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 13.878 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[3]~686'
    Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 13.964 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[4]~687'
    Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 14.050 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[5]~688'
    Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 14.136 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[6]~689'
    Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 14.222 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[7]~690'
    Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 14.308 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[8]~691'
    Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 14.394 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[9]~692'
    Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 14.480 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[10]~694'
    Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 14.566 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[11]~695'
    Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 14.652 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[12]~696'
    Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 14.738 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[13]~697'
    Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 14.824 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[14]~698'
    Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 14.910 ns; Loc. = LAB_X27_Y21; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[15]~699'
    Info: 26: + IC(0.107 ns) + CELL(0.086 ns) = 15.103 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[16]~700'
    Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 15.189 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[17]~701'
    Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 15.275 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[18]~702'
    Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 15.361 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[19]~703'
    Info: 30: + IC(0.000 ns) + CELL(0.086 ns) = 15.447 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[20]~704'
    Info: 31: + IC(0.000 ns) + CELL(0.086 ns) = 15.533 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[21]~705'
    Info: 32: + IC(0.000 ns) + CELL(0.086 ns) = 15.619 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[22]~706'
    Info: 33: + IC(0.000 ns) + CELL(0.086 ns) = 15.705 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[23]~707'
    Info: 34: + IC(0.000 ns) + CELL(0.086 ns) = 15.791 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[24]~708'
    Info: 35: + IC(0.000 ns) + CELL(0.086 ns) = 15.877 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[25]~709'
    Info: 36: + IC(0.000 ns) + CELL(0.086 ns) = 15.963 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[26]~710'
    Info: 37: + IC(0.000 ns) + CELL(0.086 ns) = 16.049 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[27]~711'
    Info: 38: + IC(0.000 ns) + CELL(0.086 ns) = 16.135 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[28]~712'
    Info: 39: + IC(0.000 ns) + CELL(0.086 ns) = 16.221 ns; Loc. = LAB_X27_Y20; Fanout = 2; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[29]~713'
    Info: 40: + IC(0.000 ns) + CELL(0.086 ns) = 16.307 ns; Loc. = LAB_X27_Y20; Fanout = 1; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[30]~714'
    Info: 41: + IC(0.000 ns) + CELL(0.506 ns) = 16.813 ns; Loc. = LAB_X27_Y20; Fanout = 1; COMB Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[31]~640'
    Info: 42: + IC(0.000 ns) + CELL(0.108 ns) = 16.921 ns; Loc. = LAB_X27_Y20; Fanout = 3; REG Node = 'avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[31]'
    Info: Total cell delay = 8.549 ns ( 50.52 % )
    Info: Total interconnect delay = 8.372 ns ( 49.48 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 7% of the available device resources. Peak interconnect usage is 25%
    Info: The peak interconnect region extends from location X22_Y12 to location X32_Y23
Info: Fitter routing operations ending: elapsed time is 00:01:06
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Started post-fitting delay annotation
Warning: Found 42 output pins without output pin load capacitance assignment
    Info: Pin "DRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_LDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_UDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_RAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_BA_0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_BA_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "TD_RESET" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "TDO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "I2C_DATA" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "I2C_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis