de2_tv.fit.smsg

DE2_TV_m_write.rar是用来去处抖动的

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Processing started: Sun Mar 30 20:55:22 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_TV -c DE2_TV
Info: Selected device EP2C35F672C8 for design "DE2_TV"
Warning: Compensate clock of PLL "SDRAM_PLL:PLL1|altpll:altpll_component|pll" has been set to clock1
Info: Implemented PLL "SDRAM_PLL:PLL1|altpll:altpll_component|pll" as Cyclone II PLL type
    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C35F672I8 is compatible
    Info: Device EP2C50F672C8 is compatible
    Info: Device EP2C50F672I8 is compatible
    Info: Device EP2C70F672C8 is compatible
    Info: Device EP2C70F672I8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location E3
    Info: Pin ~nCSO~ is reserved at location D3
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 2 pins of 62 total pins
    Info: Pin I2C_DATA not assigned to an exact location on the device
    Info: Pin I2C_CLK not assigned to an exact location on the device
Info: Automatically promoted node OSC_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_signaltap:auto_signaltap_0|trigger_in_reg
Info: Automatically promoted node SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 (placed in counter C0 of PLL_1)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node OSC_27 (placed in PIN D13 (CLK11, LVDSCLK5p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11
Info: Automatically promoted node altera_internal_jtag~UPDATEUSER 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~112
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~99
Info: Automatically promoted node avl_m_w:DUT|avl_m_w_reset_clk_domain_synch_module:avl_m_w_reset_clk_domain_synch|data_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node avl_m_w:DUT|sdram_0:the_sdram_0|active_addr[20]~426
        Info: Destination node avl_m_w:DUT|sdram_0:the_sdram_0|active_cs_n~176
        Info: Destination node avl_m_w:DUT|sdram_0:the_sdram_0|i_refs[0]
        Info: Destination node avl_m_w:DUT|sdram_0:the_sdram_0|i_refs[2]
        Info: Destination node avl_m_w:DUT|sdram_0:the_sdram_0|i_refs[1]
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|jtag_break~47
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|reset_all 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset
Info: Automatically promoted node sld_hub:sld_hub_inst|CLR_SIGNAL 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_signaltap:auto_signaltap_0|reset_all
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1]~717
        Info: Destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~182
        Info: Destination node avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183
Info: Automatically promoted node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_2 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|oDVAL~13
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[3]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[10]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[11]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[12]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[13]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[18]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[14]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[15]
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|Z_OUT[16]
        Info: Non-global destination nodes limited to 10 nodes
Info: Automatically promoted node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_1 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|ITU_656_Decoder:u4|iSkip
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_1~54
Info: Automatically promoted node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2|TD_Stable 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2|TD_Stable~107
Info: Automatically promoted node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_0~24
Info: Automatically promoted node avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|rdaclr 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~450
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Ignoring invalid fast I/O register assignments
Info: Finished register packing: elapsed time is 00:00:09
    Extra Info: Packed 2 registers into blocks of type EC
    Extra Info: Packed 68 registers into blocks of type I/O
    Extra Info: Packed 64 registers into blocks of type Embedded multiplier block
    Extra Info: Created 66 register duplicates
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 0 input, 0 output, 2 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks