cpu_0.v

DE2_TV_m_write.rar是用来去处抖动的

      else if (take_no_action_break_b)
          break_readreg <= jdo[31 : 0];
      else if (take_no_action_break_c)
          break_readreg <= jdo[31 : 0];
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          trigger_state <= 0;
      else if (1)
          if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
              trigger_state <= 0;
          else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
              trigger_state <= -1;
    end


  assign trigger_state_0 = ~trigger_state;
  assign trigger_state_1 = trigger_state;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_nios2_oci_xbrk (
                              // inputs:
                               D_en,
                               E_en,
                               E_valid,
                               F_pc,
                               M_en,
                               clk,
                               reset_n,
                               trigger_state_0,
                               trigger_state_1,
                               xbrk0,
                               xbrk1,
                               xbrk2,
                               xbrk3,
                               xbrk_ctrl0,
                               xbrk_ctrl1,
                               xbrk_ctrl2,
                               xbrk_ctrl3,

                              // outputs:
                               xbrk_break,
                               xbrk_goto0,
                               xbrk_goto1,
                               xbrk_traceoff,
                               xbrk_traceon,
                               xbrk_trigout
                            )
;

  output           xbrk_break;
  output           xbrk_goto0;
  output           xbrk_goto1;
  output           xbrk_traceoff;
  output           xbrk_traceon;
  output           xbrk_trigout;
  input            D_en;
  input            E_en;
  input            E_valid;
  input   [ 21: 0] F_pc;
  input            M_en;
  input            clk;
  input            reset_n;
  input            trigger_state_0;
  input            trigger_state_1;
  input   [ 23: 0] xbrk0;
  input   [ 23: 0] xbrk1;
  input   [ 23: 0] xbrk2;
  input   [ 23: 0] xbrk3;
  input   [  7: 0] xbrk_ctrl0;
  input   [  7: 0] xbrk_ctrl1;
  input   [  7: 0] xbrk_ctrl2;
  input   [  7: 0] xbrk_ctrl3;

  wire             D_cpu_addr_en;
  wire             E_cpu_addr_en;
  reg              E_xbrk_goto0;
  reg              E_xbrk_goto1;
  reg              E_xbrk_traceoff;
  reg              E_xbrk_traceon;
  reg              E_xbrk_trigout;
  reg              M_xbrk_goto0;
  reg              M_xbrk_goto1;
  reg              M_xbrk_traceoff;
  reg              M_xbrk_traceon;
  reg              M_xbrk_trigout;
  wire    [ 23: 0] cpu_i_address;
  wire             xbrk0_armed;
  wire             xbrk1_armed;
  wire             xbrk2_armed;
  wire             xbrk3_armed;
  reg              xbrk_break;
  wire             xbrk_break_hit;
  wire             xbrk_goto0;
  wire             xbrk_goto0_hit;
  wire             xbrk_goto1;
  wire             xbrk_goto1_hit;
  reg              xbrk_hit0;
  reg              xbrk_hit1;
  reg              xbrk_hit2;
  reg              xbrk_hit3;
  wire             xbrk_toff_hit;
  wire             xbrk_ton_hit;
  wire             xbrk_tout_hit;
  wire             xbrk_traceoff;
  wire             xbrk_traceon;
  wire             xbrk_trigout;
  assign cpu_i_address = {F_pc, 2'b00};
  assign D_cpu_addr_en = D_en;
  assign E_cpu_addr_en = E_en;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit0 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit0 <= (0 >= 1) & 
                    (cpu_i_address == xbrk0[23 : 0]);

    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit1 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit1 <= (0 >= 2) & 
                    (cpu_i_address == xbrk1[23 : 0]);

    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit2 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit2 <= (0 >= 3) & 
                    (cpu_i_address == xbrk2[23 : 0]);

    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit3 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit3 <= (0 >= 4) &
                    (cpu_i_address == xbrk3[23 : 0]);

    end


  assign xbrk_break_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[0]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[0]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[0]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[0]);

  assign xbrk_ton_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[3]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[3]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[3]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[3]);

  assign xbrk_toff_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[2]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[2]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[2]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[2]);

  assign xbrk_tout_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[1]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[1]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[1]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[1]);

  assign xbrk_goto0_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[6]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[6]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[6]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[6]);

  assign xbrk_goto1_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[7]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[7]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[7]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[7]);

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_break <= 0;
      else if (E_cpu_addr_en)
          xbrk_break <= xbrk_break_hit;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          E_xbrk_traceon <= 0;
      else if (E_cpu_addr_en)
          E_xbrk_traceon <= xbrk_ton_hit;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          E_xbrk_traceoff <= 0;
      else if (E_cpu_addr_en)
          E_xbrk_traceoff <= xbrk_toff_hit;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          E_xbrk_trigout <= 0;
      else if (E_cpu_addr_en)
          E_xbrk_trigout <= xbrk_tout_hit;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          E_xbrk_goto0 <= 0;
      else if (E_cpu_addr_en)
          E_xbrk_goto0 <= xbrk_goto0_hit;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          E_xbrk_goto1 <= 0;
      else if (E_cpu_addr_en)
          E_xbrk_goto1 <= xbrk_goto1_hit;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          M_xbrk_traceon <= 0;
      else if (M_en)
          M_xbrk_traceon <= E_xbrk_traceon & E_valid;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          M_xbrk_traceoff <= 0;
      else if (M_en)
          M_xbrk_traceoff <= E_xbrk_traceoff & E_valid;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          M_xbrk_trigout <= 0;
      else if (M_en)
          M_xbrk_trigout <= E_xbrk_trigout & E_valid;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          M_xbrk_goto0 <= 0;
      else if (M_en)
          M_xbrk_goto0 <= E_xbrk_goto0 & E_valid;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          M_xbrk_goto1 <= 0;
      else if (M_en)
          M_xbrk_goto1 <= E_xbrk_goto1 & E_valid;
    end


  assign xbrk_traceon = M_xbrk_traceon;
  assign xbrk_traceoff = M_xbrk_traceoff;
  assign xbrk_trigout = M_xbrk_trigout;
  assign xbrk_goto0 = M_xbrk_goto0;
  assign xbrk_goto1 = M_xbrk_goto1;
  assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
    (xbrk_ctrl0[5] & trigger_state_1);

  assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
    (xbrk_ctrl1[5] & trigger_state_1);

  assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
    (xbrk_ctrl2[5] & trigger_state_1);

  assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
    (xbrk_ctrl3[5] & trigger_state_1);


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_nios2_oci_match_paired (
                                      // inputs:
                                       addr,
                                       data,
                                       dbrka,
                                       dbrkb,
                                       read,
                                       write,

                                      // outputs:
                                       match_paired
                                    )
;

  output           match_paired;
  input   [ 23: 0] addr;
  input   [ 31: 0] data;
  input   [ 70: 0] dbrka;
  input   [ 70: 0] dbrkb;
  input            read;
  input            write;

  wire             match_paired;
  wire             match_paired_combinatorial;
  assign match_paired_combinatorial = (~dbrka[67]       || ((addr >= dbrka[23 : 0])            && (addr <= dbrkb[23 : 0]))) && (~dbrka[68]       || (((data ^ dbrka[63 : 32])             & dbrkb[63 : 32]) == 0)) && ((dbrka[66] & read)       || (dbrka[65] & write));
  assign match_paired = match_paired_combinatorial;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_nios2_oci_match_single (
                                      // inputs:
                                       addr,
                                       data,
                                       dbrk,
                                       read,
                                       write,

                                      // outputs:
                                       match_single
                                    )
;

  output           match_single;
  input   [ 23: 0] addr;
  input   [ 31: 0] data;
  input   [ 70: 0] dbrk;
  input            read;
  input            write;

  wire             match_single;
  wire             match_single_combinatorial;
  assign match_single_combinatorial = (~dbrk[67] || (addr == dbrk[23 : 0]))  && (~dbrk[68] || (data == dbrk[63 : 32]))  && (    (dbrk[66] & read)       || (dbrk[65] & write));
  assign match_single = match_single_combinatorial;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_nios2_oci_dbrk (
                              // inputs:
                               A_ctrl_ld,
                               A_ctrl_st,
                               A_en,
                               A_mem_baddr,
                               A_st_data,
                               A_valid,
                               A_wr_data_filtered,
                               clk,