cpu_0.v

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  output  [ 31: 0] break_readreg;
  output  [ 77: 0] dbrk0;
  output  [ 77: 0] dbrk1;
  output  [ 77: 0] dbrk2;
  output  [ 77: 0] dbrk3;
  output           dbrk_hit0_latch;
  output           dbrk_hit1_latch;
  output           dbrk_hit2_latch;
  output           dbrk_hit3_latch;
  output           trigbrktype;
  output           trigger_state_0;
  output           trigger_state_1;
  output  [ 23: 0] xbrk0;
  output  [ 23: 0] xbrk1;
  output  [ 23: 0] xbrk2;
  output  [ 23: 0] xbrk3;
  output  [  7: 0] xbrk_ctrl0;
  output  [  7: 0] xbrk_ctrl1;
  output  [  7: 0] xbrk_ctrl2;
  output  [  7: 0] xbrk_ctrl3;
  input            clk;
  input            dbrk_break;
  input            dbrk_goto0;
  input            dbrk_goto1;
  input            dbrk_hit0;
  input            dbrk_hit1;
  input            dbrk_hit2;
  input            dbrk_hit3;
  input   [ 37: 0] jdo;
  input            jrst_n;
  input            reset_n;
  input            take_action_break_a;
  input            take_action_break_b;
  input            take_action_break_c;
  input            take_no_action_break_a;
  input            take_no_action_break_b;
  input            take_no_action_break_c;
  input            xbrk_goto0;
  input            xbrk_goto1;

  wire    [  3: 0] break_a_wpr;
  wire    [  1: 0] break_a_wpr_high_bits;
  wire    [  1: 0] break_a_wpr_low_bits;
  wire    [  1: 0] break_b_rr;
  wire    [  1: 0] break_c_rr;
  reg     [ 31: 0] break_readreg;
  reg     [ 77: 0] dbrk0;
  reg     [ 77: 0] dbrk1;
  reg     [ 77: 0] dbrk2;
  reg     [ 77: 0] dbrk3;
  reg              dbrk_hit0_latch;
  reg              dbrk_hit1_latch;
  reg              dbrk_hit2_latch;
  reg              dbrk_hit3_latch;
  wire             take_action_any_break;
  reg              trigbrktype;
  reg              trigger_state;
  wire             trigger_state_0;
  wire             trigger_state_1;
  reg     [ 23: 0] xbrk0;
  reg     [ 23: 0] xbrk1;
  reg     [ 23: 0] xbrk2;
  reg     [ 23: 0] xbrk3;
  reg     [  7: 0] xbrk_ctrl0;
  reg     [  7: 0] xbrk_ctrl1;
  reg     [  7: 0] xbrk_ctrl2;
  reg     [  7: 0] xbrk_ctrl3;
  assign break_a_wpr = jdo[35 : 32];
  assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
  assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
  assign break_b_rr = jdo[33 : 32];
  assign break_c_rr = jdo[33 : 32];
  assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
  always @(posedge clk or negedge jrst_n)
    begin
      if (jrst_n == 0)
        begin
          xbrk_ctrl0 <= 0;
          xbrk_ctrl1 <= 0;
          xbrk_ctrl2 <= 0;
          xbrk_ctrl3 <= 0;
          trigbrktype <= 0;
          if (0 >= 1)
              xbrk0 <= 0;
          if (0 >= 2)
              xbrk1 <= 0;
          if (0 >= 3)
              xbrk2 <= 0;
          if (0 >= 4)
              xbrk3 <= 0;
          if (0 >= 1)
              dbrk0 <= 0;
          if (0 >= 2)
              dbrk1 <= 0;
          if (0 >= 3)
              dbrk2 <= 0;
          if (0 >= 4)
              dbrk3 <= 0;
        end
      else 
        begin
          if (take_action_any_break)
              trigbrktype <= 0;
          else if (dbrk_break)
              trigbrktype <= 1;
          if (take_action_break_a)
              case (break_a_wpr_high_bits)
              
                  2'd0: begin
                      if ((0 >= 1) && (break_a_wpr_low_bits == 2'b00))
                          xbrk0[23 : 0] <= jdo[31 : 0];
                      if ((0 >= 2) && (break_a_wpr_low_bits == 2'b01))
                          xbrk1[23 : 0] <= jdo[31 : 0];
                      if ((0 >= 3) && (break_a_wpr_low_bits == 2'b10))
                          xbrk2[23 : 0] <= jdo[31 : 0];
                      if ((0 >= 4) && (break_a_wpr_low_bits == 2'b11))
                          xbrk3[23 : 0] <= jdo[31 : 0];
                  end // 2'd0 
              
                  2'd2: begin
                      if ((0 >= 1) && (break_a_wpr_low_bits == 2'b00))
                          dbrk0[23 : 0] <= jdo[31 : 0];
                      if ((0 >= 2) && (break_a_wpr_low_bits == 2'b01))
                          dbrk1[23 : 0] <= jdo[31 : 0];
                      if ((0 >= 3) && (break_a_wpr_low_bits == 2'b10))
                          dbrk2[23 : 0] <= jdo[31 : 0];
                      if ((0 >= 4) && (break_a_wpr_low_bits == 2'b11))
                          dbrk3[23 : 0] <= jdo[31 : 0];
                  end // 2'd2 
              
                  2'd3: begin
                      if ((0 >= 1) && (break_a_wpr_low_bits == 2'b00))
                          dbrk0[63 : 32] <= jdo[31 : 0];
                      if ((0 >= 2) && (break_a_wpr_low_bits == 2'b01))
                          dbrk1[63 : 32] <= jdo[31 : 0];
                      if ((0 >= 3) && (break_a_wpr_low_bits == 2'b10))
                          dbrk2[63 : 32] <= jdo[31 : 0];
                      if ((0 >= 4) && (break_a_wpr_low_bits == 2'b11))
                          dbrk3[63 : 32] <= jdo[31 : 0];
                  end // 2'd3 
              
              endcase // break_a_wpr_high_bits
          else if (take_action_break_b)
            begin
              if ((break_b_rr == 2'b00) && (0 >= 1))
                begin
                  xbrk_ctrl0[0] <= jdo[27];
                  xbrk_ctrl0[1] <= jdo[28];
                  xbrk_ctrl0[2] <= jdo[29];
                  xbrk_ctrl0[3] <= jdo[30];
                  xbrk_ctrl0[4] <= jdo[21];
                  xbrk_ctrl0[5] <= jdo[20];
                  xbrk_ctrl0[6] <= jdo[19];
                  xbrk_ctrl0[7] <= jdo[18];
                end
              if ((break_b_rr == 2'b01) && (0 >= 2))
                begin
                  xbrk_ctrl1[0] <= jdo[27];
                  xbrk_ctrl1[1] <= jdo[28];
                  xbrk_ctrl1[2] <= jdo[29];
                  xbrk_ctrl1[3] <= jdo[30];
                  xbrk_ctrl1[4] <= jdo[21];
                  xbrk_ctrl1[5] <= jdo[20];
                  xbrk_ctrl1[6] <= jdo[19];
                  xbrk_ctrl1[7] <= jdo[18];
                end
              if ((break_b_rr == 2'b10) && (0 >= 3))
                begin
                  xbrk_ctrl2[0] <= jdo[27];
                  xbrk_ctrl2[1] <= jdo[28];
                  xbrk_ctrl2[2] <= jdo[29];
                  xbrk_ctrl2[3] <= jdo[30];
                  xbrk_ctrl2[4] <= jdo[21];
                  xbrk_ctrl2[5] <= jdo[20];
                  xbrk_ctrl2[6] <= jdo[19];
                  xbrk_ctrl2[7] <= jdo[18];
                end
              if ((break_b_rr == 2'b11) && (0 >= 4))
                begin
                  xbrk_ctrl3[0] <= jdo[27];
                  xbrk_ctrl3[1] <= jdo[28];
                  xbrk_ctrl3[2] <= jdo[29];
                  xbrk_ctrl3[3] <= jdo[30];
                  xbrk_ctrl3[4] <= jdo[21];
                  xbrk_ctrl3[5] <= jdo[20];
                  xbrk_ctrl3[6] <= jdo[19];
                  xbrk_ctrl3[7] <= jdo[18];
                end
            end
          else if (take_action_break_c)
            begin
              if ((0 >= 1) && (break_c_rr == 2'b00))
                begin
                  dbrk0[65] <= jdo[23];
                  dbrk0[66] <= jdo[24];
                  dbrk0[67] <= jdo[25];
                  dbrk0[68] <= jdo[26];
                  dbrk0[69] <= jdo[27];
                  dbrk0[70] <= jdo[28];
                  if (1)
                      dbrk0[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk0[71] <= jdo[29];
                      dbrk0[72] <= jdo[30];
                      dbrk0[73] <= jdo[31];
                    end
                  dbrk0[74] <= jdo[21];
                  dbrk0[75] <= jdo[20];
                  dbrk0[76] <= jdo[19];
                  dbrk0[77] <= jdo[18];
                end
              if ((0 >= 2) && (break_c_rr == 2'b01))
                begin
                  dbrk1[65] <= jdo[23];
                  dbrk1[66] <= jdo[24];
                  dbrk1[67] <= jdo[25];
                  dbrk1[68] <= jdo[26];
                  dbrk1[69] <= jdo[27];
                  dbrk1[70] <= jdo[28];
                  if (1)
                      dbrk1[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk1[71] <= jdo[29];
                      dbrk1[72] <= jdo[30];
                      dbrk1[73] <= jdo[31];
                    end
                  dbrk1[74] <= jdo[21];
                  dbrk1[75] <= jdo[20];
                  dbrk1[76] <= jdo[19];
                  dbrk1[77] <= jdo[18];
                end
              if ((0 >= 3) && (break_c_rr == 2'b10))
                begin
                  dbrk2[65] <= jdo[23];
                  dbrk2[66] <= jdo[24];
                  dbrk2[67] <= jdo[25];
                  dbrk2[68] <= jdo[26];
                  dbrk2[69] <= jdo[27];
                  dbrk2[70] <= jdo[28];
                  if (1)
                      dbrk2[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk2[71] <= jdo[29];
                      dbrk2[72] <= jdo[30];
                      dbrk2[73] <= jdo[31];
                    end
                  dbrk2[74] <= jdo[21];
                  dbrk2[75] <= jdo[20];
                  dbrk2[76] <= jdo[19];
                  dbrk2[77] <= jdo[18];
                end
              if ((0 >= 4) && (break_c_rr == 2'b11))
                begin
                  dbrk3[65] <= jdo[23];
                  dbrk3[66] <= jdo[24];
                  dbrk3[67] <= jdo[25];
                  dbrk3[68] <= jdo[26];
                  dbrk3[69] <= jdo[27];
                  dbrk3[70] <= jdo[28];
                  if (1)
                      dbrk3[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk3[71] <= jdo[29];
                      dbrk3[72] <= jdo[30];
                      dbrk3[73] <= jdo[31];
                    end
                  dbrk3[74] <= jdo[21];
                  dbrk3[75] <= jdo[20];
                  dbrk3[76] <= jdo[19];
                  dbrk3[77] <= jdo[18];
                end
            end
        end
    end


  always @(posedge clk)
    begin
      if (take_action_any_break)
        begin
          dbrk_hit0_latch <= 1'b0;
          dbrk_hit1_latch <= 1'b0;
          dbrk_hit2_latch <= 1'b0;
          dbrk_hit3_latch <= 1'b0;
        end
      else 
        begin
          if (dbrk_hit0 & dbrk0[69])
              dbrk_hit0_latch <= 1'b1;
          if (dbrk_hit1 & dbrk1[69])
              dbrk_hit1_latch <= 1'b1;
          if (dbrk_hit2 & dbrk2[69])
              dbrk_hit2_latch <= 1'b1;
          if (dbrk_hit3 & dbrk3[69])
              dbrk_hit3_latch <= 1'b1;
        end
    end


  always @(posedge clk or negedge jrst_n)
    begin
      if (jrst_n == 0)
          break_readreg <= 32'b0;
      else if (take_action_any_break)
          break_readreg <= jdo[31 : 0];
      else if (take_no_action_break_a)
          case (break_a_wpr_high_bits)
          
              2'd0: begin
                  case (break_a_wpr_low_bits) // synthesis full_case
                  
                      2'd0: begin
                          break_readreg <= (0 >= 1) ? xbrk0 : 32'b0;
                      end // 2'd0 
                  
                      2'd1: begin
                          break_readreg <= (0 >= 2) ? xbrk1 : 32'b0;
                      end // 2'd1 
                  
                      2'd2: begin
                          break_readreg <= (0 >= 3) ? xbrk2 : 32'b0;
                      end // 2'd2 
                  
                      2'd3: begin
                          break_readreg <= (0 >= 4) ? xbrk3 : 32'b0;
                      end // 2'd3 
                  
                  endcase // break_a_wpr_low_bits
              end // 2'd0 
          
              2'd1: begin
                  break_readreg <= 32'b0;
              end // 2'd1 
          
              2'd2: begin
                  case (break_a_wpr_low_bits) // synthesis full_case
                  
                      2'd0: begin
                          break_readreg <= (0 >= 1)  ? 
                                  dbrk0[23 : 0] : 32'b0;
                  
                      end // 2'd0 
                  
                      2'd1: begin
                          break_readreg <= (0 >= 2)  ? 
                                  dbrk1[23 : 0] : 32'b0;
                  
                      end // 2'd1 
                  
                      2'd2: begin
                          break_readreg <= (0 >= 3)  ? 
                                  dbrk2[23 : 0] : 32'b0;
                  
                      end // 2'd2 
                  
                      2'd3: begin
                          break_readreg <= (0 >= 4)  ? 
                                  dbrk3[23 : 0] : 32'b0;
                  
                      end // 2'd3 
                  
                  endcase // break_a_wpr_low_bits
              end // 2'd2 
          
              2'd3: begin
                  case (break_a_wpr_low_bits) // synthesis full_case
                  
                      2'd0: begin
                          break_readreg <= (0 >= 1)  ? 
                                  dbrk0[63 : 32] : 32'b0;
                  
                      end // 2'd0 
                  
                      2'd1: begin
                          break_readreg <= (0 >= 2)  ? 
                                  dbrk1[63 : 32] : 32'b0;
                  
                      end // 2'd1 
                  
                      2'd2: begin
                          break_readreg <= (0 >= 3)  ? 
                                  dbrk2[63 : 32] : 32'b0;
                  
                      end // 2'd2 
                  
                      2'd3: begin
                          break_readreg <= (0 >= 4)  ? 
                                  dbrk3[63 : 32] : 32'b0;
                  
                      end // 2'd3 
                  
                  endcase // break_a_wpr_low_bits
              end // 2'd3 
          
          endcase // break_a_wpr_high_bits