📄 cpu_0.v
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always @(posedge clk)
begin
if (take_action_ocimem_a)
begin
monitor_ready <= jdo[25] ? 1'b0 : monitor_ready;
monitor_error <= jdo[25] ? 1'b0 : monitor_error;
monitor_go <= jdo[23] ? 1'b1 : monitor_go;
end
else if (take_action_ocireg)
begin
monitor_ready <= ocireg_mrs ? 1'b1 : monitor_ready;
monitor_error <= ocireg_ers ? 1'b1 : monitor_error;
end
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
byteena_a,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q_a;
output [ 31: 0] q_b;
input [ 7: 0] address_a;
input [ 7: 0] address_b;
input [ 3: 0] byteena_a;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 31: 0] data_a;
input [ 31: 0] data_b;
input wren_a;
input wren_b;
wire [ 31: 0] q_a;
wire [ 31: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "Stratix",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_nios2_ocimem (
// inputs:
address,
begintransfer,
byteenable,
chipselect,
clk,
debugaccess,
jdo,
jrst_n,
resetrequest,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
oci_ram_readdata
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] oci_ram_readdata;
input [ 8: 0] address;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input resetrequest;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg;
reg [ 31: 0] MonDReg;
reg MonRd;
reg MonRd1;
reg MonWr;
wire avalon;
wire [ 31: 0] cfgdout;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] sramdout;
assign avalon = begintransfer & ~resetrequest;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
MonWr <= 1'b0;
MonRd <= 1'b0;
MonRd1 <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonRd <= 1'b1;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
MonRd <= 1'b1;
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonDReg <= jdo[34 : 3];
MonWr <= 1'b1;
end
else
begin
if (~avalon)
begin
MonWr <= 0;
MonRd <= 0;
end
if (MonRd1)
MonDReg <= MonAReg[10] ? cfgdout : sramdout;
end
MonRd1 <= MonRd;
end
end
//cpu_0_ociram_lpm_dram_bdp_component, which is an e_bdpram
cpu_0_ociram_lpm_dram_bdp_component_module cpu_0_ociram_lpm_dram_bdp_component
(
.address_a (address[7 : 0]),
.address_b (MonAReg[9 : 2]),
.byteena_a (byteenable),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (writedata),
.data_b (MonDReg[31 : 0]),
.q_a (oci_ram_readdata),
.q_b (sramdout),
.wren_a (chipselect & write & debugaccess &
~address[8]
),
.wren_b (MonWr)
);
//synthesis translate_off
`ifdef NO_PLI
defparam cpu_0_ociram_lpm_dram_bdp_component.lpm_file = "cpu_0_ociram_default_contents.dat";
`else
defparam cpu_0_ociram_lpm_dram_bdp_component.lpm_file = "cpu_0_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam cpu_0_ociram_lpm_dram_bdp_component.lpm_file = "cpu_0_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgdout = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001818 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h28000b0c :
(MonAReg[4 : 2] == 3'd5)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input chipselect;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = chipselect & write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= {32{1'b1}};
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_hit0,
dbrk_hit1,
dbrk_hit2,
dbrk_hit3,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk0,
dbrk1,
dbrk2,
dbrk3,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk0,
xbrk1,
xbrk2,
xbrk3,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
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