cpu_0.v

DE2_TV_m_write.rar是用来去处抖动的

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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_ic_data_module (
                              // inputs:
                               data,
                               rdaddress,
                               rdclken,
                               rdclock,
                               wraddress,
                               wrclock,
                               wren,

                              // outputs:
                               q
                            )
;

  parameter lpm_file = "UNUSED";


  output  [ 31: 0] q;
  input   [ 31: 0] data;
  input   [  9: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  9: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [ 31: 0] q;
  wire    [ 31: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 1024,
           the_altsyncram.numwords_b = 1024,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
           the_altsyncram.width_a = 32,
           the_altsyncram.width_b = 32,
           the_altsyncram.widthad_a = 10,
           the_altsyncram.widthad_b = 10;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 1024,
//           the_altsyncram.numwords_b = 1024,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
//           the_altsyncram.width_a = 32,
//           the_altsyncram.width_b = 32,
//           the_altsyncram.widthad_a = 10,
//           the_altsyncram.widthad_b = 10;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_ic_tag_module (
                             // inputs:
                              data,
                              rdaddress,
                              rdclken,
                              rdclock,
                              wraddress,
                              wrclock,
                              wren,

                             // outputs:
                              q
                           )
;

  parameter lpm_file = "UNUSED";


  output  [ 19: 0] q;
  input   [ 19: 0] data;
  input   [  6: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  6: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [ 19: 0] q;
  wire    [ 19: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.init_file = lpm_file,
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 128,
           the_altsyncram.numwords_b = 128,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
           the_altsyncram.width_a = 20,
           the_altsyncram.width_b = 20,
           the_altsyncram.widthad_a = 7,
           the_altsyncram.widthad_b = 7;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.init_file = lpm_file,
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 128,
//           the_altsyncram.numwords_b = 128,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
//           the_altsyncram.width_a = 20,
//           the_altsyncram.width_b = 20,
//           the_altsyncram.widthad_a = 7,
//           the_altsyncram.widthad_b = 7;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_bht_module (
                          // inputs:
                           data,
                           rdaddress,
                           rdclken,
                           rdclock,
                           wraddress,
                           wrclock,
                           wren,

                          // outputs:
                           q
                        )
;

  parameter lpm_file = "UNUSED";


  output  [  1: 0] q;
  input   [  1: 0] data;
  input   [  7: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  7: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [  1: 0] q;
  wire    [  1: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.init_file = lpm_file,
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 256,
           the_altsyncram.numwords_b = 256,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
           the_altsyncram.width_a = 2,
           the_altsyncram.width_b = 2,
           the_altsyncram.widthad_a = 8,
           the_altsyncram.widthad_b = 8;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.init_file = lpm_file,
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 256,
//           the_altsyncram.numwords_b = 256,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
//           the_altsyncram.width_a = 2,
//           the_altsyncram.width_b = 2,
//           the_altsyncram.widthad_a = 8,
//           the_altsyncram.widthad_b = 8;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_register_bank_a_module (
                                      // inputs:
                                       data,
                                       rdaddress,
                                       rdclken,
                                       rdclock,
                                       wraddress,
                                       wrclock,
                                       wren,

                                      // outputs:
                                       q
                                    )
;

  parameter lpm_file = "UNUSED";


  output  [ 31: 0] q;
  input   [ 31: 0] data;
  input   [  4: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  4: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [ 31: 0] q;
  wire    [ 31: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.init_file = lpm_file,
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 32,
           the_altsyncram.numwords_b = 32,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
           the_altsyncram.width_a = 32,
           the_altsyncram.width_b = 32,
           the_altsyncram.widthad_a = 5,
           the_altsyncram.widthad_b = 5;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),