avl_m_w_log.txt

DE2_TV_m_write.rar是用来去处抖动的

Altera SOPC Builder Version 7.00 Build 33
Copyright (c) 1999-2006 Altera Corporation.  All rights reserved.


# 2008.03.30 20:42:54 (*) mk_custom_sdk starting
# 2008.03.30 20:42:54 (*) Reading project D:/DE2_TV_m_write/avl_m_w.ptf.

# 2008.03.30 20:42:55 (*) Finding all CPUs
# 2008.03.30 20:42:55 (*) Finding all available components
# 2008.03.30 20:42:55 (*) Reading D:/DE2_TV_m_write/.sopc_builder/install.ptf

# 2008.03.30 20:42:55 (*) Found 64 components

# 2008.03.30 20:42:57 (*) Finding all peripherals

# 2008.03.30 20:42:57 (*) Finding software components

# 2008.03.30 20:42:58 (*) (Legacy SDK Generation Skipped)
# 2008.03.30 20:42:58 (*) (All TCL Script Generation Skipped)
# 2008.03.30 20:42:58 (*) (No Libraries Built)
# 2008.03.30 20:42:58 (*) (Contents Generation Skipped)
# 2008.03.30 20:42:58 (*) mk_custom_sdk finishing

# 2008.03.30 20:42:58 (*) Starting generation for system: avl_m_w.

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# 2008.03.30 20:43:03 (*) Running Generator Program for cpu_0

# 2008.03.30 20:43:04 (*)   IP functional simulation model enabled: Uncheck System Generation Simulation box for faster generation if HDL Simulation not required.
# 2008.03.30 20:43:07 (*)   Checking for plaintext license.
# 2008.03.30 20:43:08 (*)   Plaintext license found.
# 2008.03.30 20:43:24 (*)   Creating plain-text HDL

# 2008.03.30 20:43:38 (*) Running Generator Program for jtag_uart_0

# 2008.03.30 20:43:41 (*) Running Generator Program for sdram_0

# 2008.03.30 20:43:44 (*) Running Generator Program for de2_tv2_0


# 2008.03.30 20:43:48 (*) c:/altera/70/quartus/sopc_builder/bin/gtf-generate --output-directory=./de2_tv2_0_map --gtf=c:/altera/70/quartus/sopc_builder/bin/gtf/system.h.gtf --stf=./de2_tv2_0_project.stf

# 2008.03.30 20:43:48 (*) c:/altera/70/quartus//bin/cygwin/bin/sh.exe -c "sopc_directory=c:/altera/70/quartus/sopc_builder; . c:/altera/70/quartus/sopc_builder/bin/nios_sh; c:/altera/70/quartus/sopc_builder/bin/gtf-generate --output-directory=./de2_tv2_0_map --gtf=c:/altera/70/quartus/sopc_builder/bin/gtf/system.h.gtf --stf=./de2_tv2_0_project.stf"


# 2008.03.30 20:44:00 (*) rm ./de2_tv2_0_project.stf

# 2008.03.30 20:44:00 (*) c:/altera/70/quartus//bin/cygwin/bin/sh.exe -c "sopc_directory=c:/altera/70/quartus/sopc_builder; . c:/altera/70/quartus/sopc_builder/bin/nios_sh; rm ./de2_tv2_0_project.stf"

# 2008.03.30 20:44:04 (*) Generated memory map "./de2_tv2_0_map/system.h"

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# 2008.03.30 20:44:08 (*) Running Test Generator Program for sdram_0

# 2008.03.30 20:44:11 (*) Making arbitration and system (top) modules.

# 2008.03.30 20:44:22 (*) Generating Quartus symbol for top level: avl_m_w

# 2008.03.30 20:44:22 (*) Symbol D:/DE2_TV_m_write/avl_m_w.bsf already exists, no need to regenerate
# 2008.03.30 20:44:22 (*) Creating command-line system-generation script: D:/DE2_TV_m_write/avl_m_w_generation_script

# 2008.03.30 20:44:22 (*) Running setup for HDL simulator: modelsim


Building ModelSim Project

Reading C:/Modeltech_6.0c/tcl/vsim/pref.tcl 

Reading D:/DE2_TV_m_write/avl_m_w_sim/modelsim.tcl 
c:/altera/70/quartus/sopc_builder
c:/altera/70/quartus//bin/perl
Sopc_Builder Directory: c:/altera/70/quartus/sopc_builder 

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 
@@ 
@@ setup_sim.do 
@@ 
@@ Defined aliases: 
@@ 
@@ s -- Load all design (HDL) files. 
@@ re-vlog/re-vcom and re-vsim the design. 
@@ 
@@ c -- Re-compile memory contents. 
@@ Builds C- and assembly-language programs 
@@ (and associated simulation data-files 
@@ such as UART simulation strings) for 
@@ refreshing memory contents. 
@@ Does NOT re-generate hardware (HDL) files 
@@ ONLY WORKS WITH LEGACY SDK (Not the Nios IDE) 
@@ 
@@ w -- Sets-up waveforms for this design 

@@ Each SOPC-Builder component may have 
@@ signals 'marked' for display during 
@@ simulation. This command opens a wave- 
@@ window containing all such signals. 
@@ 

@@ l -- Sets-up list waveforms for this design 
@@ Each SOPC-Builder component may have 
@@ signals 'marked' for listing during 
@@ simulation. This command opens a list- 
@@ window containing all such signals. 
@@ 
@@ jtag_uart_0_log -- display interactive output window for jtag_uart_0 
@@ 
@@ h -- print this message 
@@ 
@@ 


# 6.0c


# do create_avl_m_w_project.do 

# Loading project avl_m_w_sim

# 2008.03.30 20:44:31 (*) Setting up Quartus with avl_m_w_setup_quartus.tcl
c:/altera/70/quartus/bin/quartus_sh -t avl_m_w_setup_quartus.tcl


Info: *******************************************************************
Info: Running Quartus II Shell
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to
 the 
    Info: applicable agreement for further details.
    Info: Processing started: Sun Mar 30 20:44:32 2008
Info: Command: quartus_sh -t avl_m_w_setup_quartus.tcl
Info: Evaluation of Tcl script avl_m_w_setup_quartus.tcl was successful
Info: Quartus II Shell was successful. 0 errors, 0 warnings
    Info: Allocated 42 megabytes of memory during processing
    Info: Processing ended: Sun Mar 30 20:44:33 2008
    Info: Elapsed time: 00:00:01

# 2008.03.30 20:44:34 (*) Completed generation for system: avl_m_w.
# 2008.03.30 20:44:34 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : D:/DE2_TV_m_write/avl_m_w.ptf 
  System HDL Model : D:/DE2_TV_m_write/avl_m_w.v 
  System Generation Script : D:/DE2_TV_m_write/avl_m_w_generation_script 
  HDL Simulation Directory : D:/DE2_TV_m_write/avl_m_w_sim 

# 2008.03.30 20:44:34 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


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