wave_presets.do

DE2_TV_m_write.rar是用来去处抖动的

# Display signals from module cpu_0
add wave -noupdate -divider {cpu_0}
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/i_readdata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/i_readdatavalid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/i_waitrequest
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/i_address
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/i_read
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/clk
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/reset_n
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_readdata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_waitrequest
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_irq
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_address
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_byteenable
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_read
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_write
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/d_writedata
add wave -noupdate -divider {base pipeline}
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/clk
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/reset_n
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_stall
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/A_stall
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/F_pcb_nxt
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/F_pcb
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_pcb
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/E_pcb
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/M_pcb
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/A_pcb
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/W_pcb
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu_0/F_vinst
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu_0/D_vinst
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu_0/E_vinst
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu_0/M_vinst
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu_0/A_vinst
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu_0/W_vinst
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/F_inst_ram_hit
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/F_issue
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/F_kill
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_kill
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_refetch
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_issue
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/E_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/M_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/A_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/W_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/W_wr_dst_reg
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/W_dst_regnum
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/W_wr_data
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_en
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/E_en
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/M_en
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/A_en
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/F_iw
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/D_iw
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/E_iw
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/E_valid_prior_to_hbreak
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/M_pipe_flush
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/M_pipe_flush_baddr
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/intr_req
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/A_ienable_reg
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/A_status_reg_pie
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu_0/E_valid_prior_to_hbreak


# Display signals from module jtag_uart_0
add wave -noupdate -divider {jtag_uart_0}
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_jtag_uart_0/av_address
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/av_chipselect
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/av_irq
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/av_read_n
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_jtag_uart_0/av_readdata
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/av_waitrequest
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/av_write_n
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_jtag_uart_0/av_writedata
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/dataavailable
add wave -noupdate -format Logic /test_bench/DUT/the_jtag_uart_0/readyfordata


# Display signals from module sdram_0
add wave -noupdate -divider {sdram_0}
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/az_addr
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/az_be_n
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/az_cs
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/az_data
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/az_rd_n
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/az_wr_n
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/clk
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/za_data
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/za_valid
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/za_waitrequest
add wave -noupdate -format Literal -radix ascii /test_bench/DUT/the_sdram_0/CODE
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/zs_addr
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/zs_ba
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/zs_cs_n
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/zs_ras_n
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/zs_cas_n
add wave -noupdate -format Logic /test_bench/DUT/the_sdram_0/zs_we_n
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/zs_dq
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_sdram_0/zs_dqm


configure wave -justifyvalue right
configure wave -signalnamewidth 1
TreeUpdate [SetDefaultTree]