de2_tv.v

DE2_TV_m_write.rar是用来去处抖动的

module DE2_TV
  (
		//	Onboard Oscilator	 
		OSC_27,
		OSC_50,
		EXT_CLOCK,
		//	Push Button
		KEY,
		//	SDRAM Interface
		DRAM_DQ,	//	16 Bits
		DRAM_ADDR,	//	12 Bits
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,	
		//	I2C
		I2C_DATA,
		I2C_CLK,
		TD_RESET,
		TD_DATA,
		TD_HS,
		TD_VS,
		TCK,
		TCS,
		TDI,
		TDO,
		
	);

input			EXT_CLOCK;
input  			TDI;				
input  			TCK;				
input  			TCS;					
output 			TDO;					
input	[7:0]	TD_DATA;  
input           TD_HS;
input           TD_VS;  
//	On Board Oscilator
input			OSC_27;
input			OSC_50;
//	Push Button
input	[3:0]	KEY;

//	SDRAM Interface
inout	[15:0]	DRAM_DQ;	// 16 Bits
output	[11:0]	DRAM_ADDR;	// 12 Bits
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

//	I2C
inout			I2C_DATA;
inout			I2C_CLK;

output			TD_RESET;

wire			CPU_RESET;
wire            OSC_100;
wire            OSC_27;

SDRAM_PLL 	PLL1	(
                           .inclk0  (OSC_50),
                           .c1      (OSC_100)
                     );

system_Reset	rst		(OSC_100,CPU_RESET);
				

avl_m_w  DUT
    (
      .EXT_CLOCK_to_the_de2_tv2_0         (EXT_CLOCK_),
      .I2C_SCLK_from_the_de2_tv2_0        (I2C_SCLK),
      .I2C_SDAT_to_and_from_the_de2_tv2_0 (I2C_SDAT),
      .KEY_to_the_de2_tv2_0               (KEY),
      .OSC_27_to_the_de2_tv2_0            (OSC_27),
      .OSC_50_to_the_de2_tv2_0            (OSC_50),
      .TCK_to_the_de2_tv2_0               (TCK),
      .TCS_to_the_de2_tv2_0               (TCS),
      .TDI_to_the_de2_tv2_0               (TDI),
      .TDO_from_the_de2_tv2_0             (TDO),
      .TD_DATA_to_the_de2_tv2_0           (TD_DATA),
      .TD_HS_to_the_de2_tv2_0             (TD_HS),
      .TD_RESET_from_the_de2_tv2_0        (TD_RESET),
      .TD_VS_to_the_de2_tv2_0             (TD_VS),
      .clk                                (OSC_100),
      .reset_n                            (CPU_RESET),
      .zs_addr_from_the_sdram_0           (DRAM_ADDR),
      .zs_ba_from_the_sdram_0             ({DRAM_BA_1,DRAM_BA_0}),
      .zs_cas_n_from_the_sdram_0          (DRAM_CAS_N),
      .zs_cke_from_the_sdram_0            (DRAM_CKE),
      .zs_cs_n_from_the_sdram_0           (DRAM_CS_N),
      .zs_dq_to_and_from_the_sdram_0      (DRAM_DQ),
      .zs_dqm_from_the_sdram_0            ({DRAM_UDQM,DRAM_LDQM}),
      .zs_ras_n_from_the_sdram_0          (DRAM_RAS_N),
      .zs_we_n_from_the_sdram_0           (DRAM_WE_N)
);
endmodule