altsyncram_qh52.tdf

DE2_TV_m_write.rar是用来去处抖动的

--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="RESTRUCTURE" DEVICE_FAMILY="Cyclone II" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_B=4 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" address_a address_b byteena_b clock0 clock1 clocken0 clocken1 data_a data_b q_a q_b wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.0 cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION altsyncram_a682 (address_a[9..0], address_b[9..0], byteena_b[3..0], clock0, clock1, clocken0, clocken1, data_a[31..0], data_b[31..0], wren_a, wren_b)
RETURNS ( q_a[31..0], q_b[31..0]);

--synthesis_resources = M4K 8 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_qh52
( 
	address_a[8..0]	:	input;
	address_b[8..0]	:	input;
	byteena_b[3..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken0	:	input;
	clocken1	:	input;
	data_a[31..0]	:	input;
	data_b[31..0]	:	input;
	q_a[31..0]	:	output;
	q_b[31..0]	:	output;
	wren_b	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_a682;
	wren_a	: NODE;

BEGIN 
	altsyncram1.address_a[] = ( address_a[8..2], B"0", address_a[1..0]);
	altsyncram1.address_b[] = ( address_b[8..2], B"0", address_b[1..0]);
	altsyncram1.byteena_b[] = byteena_b[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = clock1;
	altsyncram1.clocken0 = clocken0;
	altsyncram1.clocken1 = clocken1;
	altsyncram1.data_a[] = data_a[];
	altsyncram1.data_b[] = data_b[];
	altsyncram1.wren_a = wren_a;
	altsyncram1.wren_b = wren_b;
	q_a[] = altsyncram1.q_a[];
	q_b[] = altsyncram1.q_b[];
	wren_a = GND;
END;
--VALID FILE