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📄 dffpipe_re9.tdf

📁 DE2_TV_m_write.rar是用来去处抖动的
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--dffpipe DELAY=2 WIDTH=11 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 7.0 cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


--  Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = reg 22 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_re9
( 
	clock	:	input;
	clrn	:	input;
	d[10..0]	:	input;
	q[10..0]	:	output;
) 
VARIABLE 
	dffe6a[10..0] : dffe;
	dffe7a[10..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe6a[].clk = clock;
	dffe6a[].clrn = clrn;
	dffe6a[].d = (d[] & (! sclr));
	dffe6a[].ena = ena;
	dffe6a[].prn = prn;
	dffe7a[].clk = clock;
	dffe7a[].clrn = clrn;
	dffe7a[].d = (dffe6a[].q & (! sclr));
	dffe7a[].ena = ena;
	dffe7a[].prn = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe7a[].q;
	sclr = GND;
END;
--VALID FILE

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