de2_tv.map.qmsg

DE2_TV_m_write.rar是用来去处抖动的

{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "DE2_TV DE2_TV.v(34) " "Warning (10238): Verilog Module Declaration warning at DE2_TV.v(34): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"DE2_TV\"" {  } { { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 34 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_TV.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_TV.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_TV " "Info: Found entity 1: DE2_TV" {  } { { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_AV_Config.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_AV_Config " "Info: Found entity 1: I2C_AV_Config" {  } { { "I2C_AV_Config.v" "" { Text "D:/DE2_TV_m_write/I2C_AV_Config.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Info: Found entity 1: I2C_Controller" {  } { { "I2C_Controller.v" "" { Text "D:/DE2_TV_m_write/I2C_Controller.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PLL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file PLL.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Info: Found entity 1: PLL" {  } { { "PLL.v" "" { Text "D:/DE2_TV_m_write/PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "D:/DE2_TV_m_write/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Info: Found entity 1: SEG7_LUT_8" {  } { { "SEG7_LUT_8.v" "" { Text "D:/DE2_TV_m_write/SEG7_LUT_8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "YUV422_to_444.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file YUV422_to_444.v" { { "Info" "ISGN_ENTITY_NAME" "1 YUV422_to_444 " "Info: Found entity 1: YUV422_to_444" {  } { { "YUV422_to_444.v" "" { Text "D:/DE2_TV_m_write/YUV422_to_444.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TD_Detect.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file TD_Detect.v" { { "Info" "ISGN_ENTITY_NAME" "1 TD_Detect " "Info: Found entity 1: TD_Detect" {  } { { "TD_Detect.v" "" { Text "D:/DE2_TV_m_write/TD_Detect.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ITU_656_Decoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ITU_656_Decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 ITU_656_Decoder " "Info: Found entity 1: ITU_656_Decoder" {  } { { "ITU_656_Decoder.v" "" { Text "D:/DE2_TV_m_write/ITU_656_Decoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA_Ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGA_Ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Ctrl " "Info: Found entity 1: VGA_Ctrl" {  } { { "VGA_Ctrl.v" "" { Text "D:/DE2_TV_m_write/VGA_Ctrl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/DE2_TV_m_write/avar.v " "Warning: Can't analyze file -- file D:/DE2_TV_m_write/avar.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_TV " "Info: Elaborating entity \"DE2_TV\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "DRAM_CLK DE2_TV.v(61) " "Warning (10034): Output port \"DRAM_CLK\" at DE2_TV.v(61) has no driver" {  } { { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 61 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SDRAM_PLL.v 1 1 " "Warning: Using design file SDRAM_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SDRAM_PLL " "Info: Found entity 1: SDRAM_PLL" {  } { { "SDRAM_PLL.v" "" { Text "D:/DE2_TV_m_write/SDRAM_PLL.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SDRAM_PLL SDRAM_PLL:PLL1 " "Info: Elaborating entity \"SDRAM_PLL\" for hierarchy \"SDRAM_PLL:PLL1\"" {  } { { "DE2_TV.v" "PLL1" { Text "D:/DE2_TV_m_write/DE2_TV.v" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 454 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll SDRAM_PLL:PLL1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"SDRAM_PLL:PLL1\|altpll:altpll_component\"" {  } { { "SDRAM_PLL.v" "altpll_component" { Text "D:/DE2_TV_m_write/SDRAM_PLL.v" 91 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "SDRAM_PLL:PLL1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"SDRAM_PLL:PLL1\|altpll:altpll_component\"" {  } { { "SDRAM_PLL.v" "" { Text "D:/DE2_TV_m_write/SDRAM_PLL.v" 91 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "system_Reset.v 1 1 " "Warning: Using design file system_Reset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 system_Reset " "Info: Found entity 1: system_Reset" {  } { { "system_Reset.v" "" { Text "D:/DE2_TV_m_write/system_Reset.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_Reset system_Reset:rst " "Info: Elaborating entity \"system_Reset\" for hierarchy \"system_Reset:rst\"" {  } { { "DE2_TV.v" "rst" { Text "D:/DE2_TV_m_write/DE2_TV.v" 79 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 system_Reset.v(10) " "Warning (10230): Verilog HDL assignment warning at system_Reset.v(10): truncated value with size 32 to match size of target (16)" {  } { { "system_Reset.v" "" { Text "D:/DE2_TV_m_write/system_Reset.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "avl_m_w.v 10 10 " "Warning: Using design file avl_m_w.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_jtag_debug_module_arbitrator " "Info: Found entity 1: cpu_0_jtag_debug_module_arbitrator" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_data_master_arbitrator " "Info: Found entity 2: cpu_0_data_master_arbitrator" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 441 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_instruction_master_arbitrator " "Info: Found entity 3: cpu_0_instruction_master_arbitrator" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 683 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 de2_tv2_0_avalon_master_0_arbitrator " "Info: Found entity 4: de2_tv2_0_avalon_master_0_arbitrator" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 955 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 avl_m_w_reset_clk_domain_synch_module " "Info: Found entity 5: avl_m_w_reset_clk_domain_synch_module" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 1097 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_0_avalon_jtag_slave_arbitrator " "Info: Found entity 6: jtag_uart_0_avalon_jtag_slave_arbitrator" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 1142 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module " "Info: Found entity 7: rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 1415 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module " "Info: Found entity 8: rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 1763 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 sdram_0_s1_arbitrator " "Info: Found entity 9: sdram_0_s1_arbitrator" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2111 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 avl_m_w " "Info: Found entity 10: avl_m_w" {  } { { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2672 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "avl_m_w avl_m_w:DUT " "Info: Elaborating entity \"avl_m_w\" for hierarchy \"avl_m_w:DUT\"" {  } { { "DE2_TV.v" "DUT" { Text "D:/DE2_TV_m_write/DE2_TV.v" 109 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_jtag_debug_module_arbitrator avl_m_w:DUT\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module " "Info: Elaborating entity \"cpu_0_jtag_debug_module_arbitrator\" for hierarchy \"avl_m_w:DUT\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\"" {  } { { "avl_m_w.v" "the_cpu_0_jtag_debug_module" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2879 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}