de2_tv.map.qmsg

DE2_TV_m_write.rar是用来去处抖动的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Web Edition " "Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 30 20:52:19 2008 " "Info: Processing started: Sun Mar 30 20:52:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_TV -c DE2_TV " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_TV -c DE2_TV" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "DE2_TV2.v(88) " "Warning (10268): Verilog HDL information at DE2_TV2.v(88): Always Construct contains both blocking and non-blocking assignments" {  } { { "DE2_TV2.v" "" { Text "D:/DE2_TV_m_write/DE2_TV2.v" 88 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_TV2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_TV2.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_TV2 " "Info: Found entity 1: DE2_TV2" {  } { { "DE2_TV2.v" "" { Text "D:/DE2_TV_m_write/DE2_TV2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "write_FIFO1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file write_FIFO1.v" { { "Info" "ISGN_ENTITY_NAME" "1 write_FIFO1 " "Info: Found entity 1: write_FIFO1" {  } { { "write_FIFO1.v" "" { Text "D:/DE2_TV_m_write/write_FIFO1.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "VGA_X DE2_TV1.v(144) " "Warning (10236): Verilog HDL Implicit Net warning at DE2_TV1.v(144): created implicit net for \"VGA_X\"" {  } { { "DE2_TV1.v" "" { Text "D:/DE2_TV_m_write/DE2_TV1.v" 144 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_TV1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_TV1.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_TV1 " "Info: Found entity 1: DE2_TV1" {  } { { "DE2_TV1.v" "" { Text "D:/DE2_TV_m_write/DE2_TV1.v" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TP_RAM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file TP_RAM.v" { { "Info" "ISGN_ENTITY_NAME" "1 TP_RAM " "Info: Found entity 1: TP_RAM" {  } { { "TP_RAM.v" "" { Text "D:/DE2_TV_m_write/TP_RAM.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DIV.v" { { "Info" "ISGN_ENTITY_NAME" "1 DIV " "Info: Found entity 1: DIV" {  } { { "DIV.v" "" { Text "D:/DE2_TV_m_write/DIV.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/Sdram_RD_FIFO.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_RD_FIFO.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_RD_FIFO " "Info: Found entity 1: Sdram_RD_FIFO" {  } { { "Sdram_Control_4Port/Sdram_RD_FIFO.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/Sdram_RD_FIFO.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/Sdram_WR_FIFO.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_WR_FIFO.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_WR_FIFO " "Info: Found entity 1: Sdram_WR_FIFO" {  } { { "Sdram_Control_4Port/Sdram_WR_FIFO.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/Sdram_WR_FIFO.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/command.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Info: Found entity 1: command" {  } { { "Sdram_Control_4Port/command.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/command.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/control_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Info: Found entity 1: control_interface" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/control_interface.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 sdr_data_path.v(26) " "Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(26): truncated literal to match 1 bits" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/sdr_data_path.v" 26 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/sdr_data_path.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Info: Found entity 1: sdr_data_path" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/sdr_data_path.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/Sdram_Control_4Port.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_Control_4Port.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_Control_4Port " "Info: Found entity 1: Sdram_Control_4Port" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/Sdram_Control_4Port.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sdram_Control_4Port/Sdram_PLL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_PLL.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_PLL " "Info: Found entity 1: Sdram_PLL" {  } { { "Sdram_Control_4Port/Sdram_PLL.v" "" { Text "D:/DE2_TV_m_write/Sdram_Control_4Port/Sdram_PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MAC_3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MAC_3.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAC_3 " "Info: Found entity 1: MAC_3" {  } { { "MAC_3.v" "" { Text "D:/DE2_TV_m_write/MAC_3.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reset_Delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "Reset_Delay.v" "" { Text "D:/DE2_TV_m_write/Reset_Delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "17 YCbCr2RGB.v(124) " "Warning (10229): Verilog HDL Expression warning at YCbCr2RGB.v(124): truncated literal to match 17 bits" {  } { { "YCbCr2RGB.v" "" { Text "D:/DE2_TV_m_write/YCbCr2RGB.v" 124 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "YCbCr2RGB.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file YCbCr2RGB.v" { { "Info" "ISGN_ENTITY_NAME" "1 YCbCr2RGB " "Info: Found entity 1: YCbCr2RGB" {  } { { "YCbCr2RGB.v" "" { Text "D:/DE2_TV_m_write/YCbCr2RGB.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "EXT_CLOCK_ DE2_TV.v(84) " "Warning (10236): Verilog HDL Implicit Net warning at DE2_TV.v(84): created implicit net for \"EXT_CLOCK_\"" {  } { { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 84 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "I2C_SCLK DE2_TV.v(85) " "Warning (10236): Verilog HDL Implicit Net warning at DE2_TV.v(85): created implicit net for \"I2C_SCLK\"" {  } { { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 85 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "I2C_SDAT DE2_TV.v(86) " "Warning (10236): Verilog HDL Implicit Net warning at DE2_TV.v(86): created implicit net for \"I2C_SDAT\"" {  } { { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 86 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}