de2_tv.tan.qmsg

DE2_TV_m_write.rar是用来去处抖动的

{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "DLY0 " "Warning: Clock Setting \"DLY0\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 register avl_m_w:DUT\|de2_tv2_0:the_de2_tv2_0\|DE2_TV2:the_DE2_TV2\|m_write register avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[27\] -2.697 ns " "Info: Slack time is -2.697 ns for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" between source register \"avl_m_w:DUT\|de2_tv2_0:the_de2_tv2_0\|DE2_TV2:the_DE2_TV2\|m_write\" and destination register \"avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[27\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "6.985 ns + Largest register register " "Info: + Largest register to register requirement is 6.985 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.216 ns + " "Info: + Setup relationship between source and destination is 7.216 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.216 ns " "Info: + Latch edge is 7.216 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.784 ns  50 " "Info: Clock period of Destination clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.784 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source OSC_50 20.000 ns 10.000 ns inverted 50 " "Info: Clock period of Source clock \"OSC_50\" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.033 ns + Largest " "Info: + Largest clock skew is 0.033 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 3.222 ns + Shortest register " "Info: + Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 3.222 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 1.382 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3138 " "Info: 2: + IC(1.382 ns) + CELL(0.000 ns) = 1.382 ns; Loc. = CLKCTRL_G3; Fanout = 3138; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.666 ns) 3.222 ns avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[27\] 3 REG LCFF_X17_Y12_N21 1 " "Info: 3: + IC(1.174 ns) + CELL(0.666 ns) = 3.222 ns; Loc. = LCFF_X17_Y12_N21; Fanout = 1; REG Node = 'avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[27\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "sdram_0.v" "" { Text "D:/DE2_TV_m_write/sdram_0.v" 125 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.67 % ) " "Info: Total cell delay = 0.666 ns ( 20.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.556 ns ( 79.33 % ) " "Info: Total interconnect delay = 2.556 ns ( 79.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } { 0.000ns 1.382ns 1.174ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 source 3.189 ns - Longest register " "Info: - Longest clock path from clock \"OSC_50\" to source register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'OSC_50'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 1470 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 1470; COMB Node = 'OSC_50~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_TV.v" "" { Text "D:/DE2_TV_m_write/DE2_TV.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.666 ns) 3.189 ns avl_m_w:DUT\|de2_tv2_0:the_de2_tv2_0\|DE2_TV2:the_DE2_TV2\|m_write 3 REG LCFF_X23_Y11_N15 8 " "Info: 3: + IC(1.174 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X23_Y11_N15; Fanout = 8; REG Node = 'avl_m_w:DUT\|de2_tv2_0:the_de2_tv2_0\|DE2_TV2:the_DE2_TV2\|m_write'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } "NODE_NAME" } } { "DE2_TV2.v" "" { Text "D:/DE2_TV_m_write/DE2_TV2.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.69 % ) " "Info: Total cell delay = 1.776 ns ( 55.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.413 ns ( 44.31 % ) " "Info: Total interconnect delay = 1.413 ns ( 44.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { OSC_50 OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } { 0.000ns 1.382ns 1.174ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { OSC_50 OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "DE2_TV2.v" "" { Text "D:/DE2_TV_m_write/DE2_TV2.v" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "sdram_0.v" "" { Text "D:/DE2_TV_m_write/sdram_0.v" 125 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } { 0.000ns 1.382ns 1.174ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { OSC_50 OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.682 ns - Longest register register " "Info: - Longest register to register delay is 9.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns avl_m_w:DUT\|de2_tv2_0:the_de2_tv2_0\|DE2_TV2:the_DE2_TV2\|m_write 1 REG LCFF_X23_Y11_N15 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y11_N15; Fanout = 8; REG Node = 'avl_m_w:DUT\|de2_tv2_0:the_de2_tv2_0\|DE2_TV2:the_DE2_TV2\|m_write'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } "NODE_NAME" } } { "DE2_TV2.v" "" { Text "D:/DE2_TV_m_write/DE2_TV2.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|de2_tv2_0_avalon_master_0_arbiterlock~13 2 COMB LCCOMB_X23_Y11_N14 3 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X23_Y11_N14; Fanout = 3; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|de2_tv2_0_avalon_master_0_arbiterlock~13'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|de2_tv2_0_avalon_master_0_arbiterlock~13 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2234 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.624 ns) + CELL(0.370 ns) 1.387 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|cpu_0_data_master_qualified_request_sdram_0_s1~198 3 COMB LCCOMB_X22_Y11_N26 1 " "Info: 3: + IC(0.624 ns) + CELL(0.370 ns) = 1.387 ns; Loc. = LCCOMB_X22_Y11_N26; Fanout = 1; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|cpu_0_data_master_qualified_request_sdram_0_s1~198'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|de2_tv2_0_avalon_master_0_arbiterlock~13 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.206 ns) 2.615 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|cpu_0_data_master_qualified_request_sdram_0_s1 4 COMB LCCOMB_X20_Y11_N2 6 " "Info: 4: + IC(1.022 ns) + CELL(0.206 ns) = 2.615 ns; Loc. = LCCOMB_X20_Y11_N2; Fanout = 6; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|cpu_0_data_master_qualified_request_sdram_0_s1'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.228 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.596 ns) 3.609 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|Add2~126 5 COMB LCCOMB_X20_Y11_N12 2 " "Info: 5: + IC(0.398 ns) + CELL(0.596 ns) = 3.609 ns; Loc. = LCCOMB_X20_Y11_N12; Fanout = 2; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|Add2~126'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2529 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.799 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|Add2~128 6 COMB LCCOMB_X20_Y11_N14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.190 ns) = 3.799 ns; Loc. = LCCOMB_X20_Y11_N14; Fanout = 2; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|Add2~128'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~128 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2529 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.305 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|Add2~129 7 COMB LCCOMB_X20_Y11_N16 3 " "Info: 7: + IC(0.000 ns) + CELL(0.506 ns) = 4.305 ns; Loc. = LCCOMB_X20_Y11_N16; Fanout = 3; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|Add2~129'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~128 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~129 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2529 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.366 ns) 5.370 ns avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|cpu_0_instruction_master_granted_sdram_0_s1~66 8 COMB LCCOMB_X19_Y11_N14 40 " "Info: 8: + IC(0.699 ns) + CELL(0.366 ns) = 5.370 ns; Loc. = LCCOMB_X19_Y11_N14; Fanout = 40; COMB Node = 'avl_m_w:DUT\|sdram_0_s1_arbitrator:the_sdram_0_s1\|cpu_0_instruction_master_granted_sdram_0_s1~66'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.065 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~129 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~66 } "NODE_NAME" } } { "avl_m_w.v" "" { Text "D:/DE2_TV_m_write/avl_m_w.v" 2168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.651 ns) 6.674 ns avl_m_w:DUT\|sdram_0:the_sdram_0\|comb~12 9 COMB LCCOMB_X20_Y11_N20 8 " "Info: 9: + IC(0.653 ns) + CELL(0.651 ns) = 6.674 ns; Loc. = LCCOMB_X20_Y11_N20; Fanout = 8; COMB Node = 'avl_m_w:DUT\|sdram_0:the_sdram_0\|comb~12'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~66 avl_m_w:DUT|sdram_0:the_sdram_0|comb~12 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.370 ns) 7.435 ns avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[38\]~1162 10 COMB LCCOMB_X20_Y11_N26 41 " "Info: 10: + IC(0.391 ns) + CELL(0.370 ns) = 7.435 ns; Loc. = LCCOMB_X20_Y11_N26; Fanout = 41; COMB Node = 'avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[38\]~1162'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.761 ns" { avl_m_w:DUT|sdram_0:the_sdram_0|comb~12 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~1162 } "NODE_NAME" } } { "sdram_0.v" "" { Text "D:/DE2_TV_m_write/sdram_0.v" 125 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.392 ns) + CELL(0.855 ns) 9.682 ns avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[27\] 11 REG LCFF_X17_Y12_N21 1 " "Info: 11: + IC(1.392 ns) + CELL(0.855 ns) = 9.682 ns; Loc. = LCFF_X17_Y12_N21; Fanout = 1; REG Node = 'avl_m_w:DUT\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|entry_1\[27\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.247 ns" { avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~1162 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "sdram_0.v" "" { Text "D:/DE2_TV_m_write/sdram_0.v" 125 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.503 ns ( 46.51 % ) " "Info: Total cell delay = 4.503 ns ( 46.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.179 ns ( 53.49 % ) " "Info: Total interconnect delay = 5.179 ns ( 53.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.682 ns" { avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|de2_tv2_0_avalon_master_0_arbiterlock~13 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~128 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~129 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~66 avl_m_w:DUT|sdram_0:the_sdram_0|comb~12 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~1162 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.682 ns" { avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|de2_tv2_0_avalon_master_0_arbiterlock~13 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~128 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~129 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~66 avl_m_w:DUT|sdram_0:the_sdram_0|comb~12 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~1162 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } { 0.000ns 0.000ns 0.624ns 1.022ns 0.398ns 0.000ns 0.000ns 0.699ns 0.653ns 0.391ns 1.392ns } { 0.000ns 0.393ns 0.370ns 0.206ns 0.596ns 0.190ns 0.506ns 0.366ns 0.651ns 0.370ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.222 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } { 0.000ns 1.382ns 1.174ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { OSC_50 OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write } { 0.000ns 0.000ns 0.239ns 1.174ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.682 ns" { avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|de2_tv2_0_avalon_master_0_arbiterlock~13 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~128 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~129 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~66 avl_m_w:DUT|sdram_0:the_sdram_0|comb~12 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~1162 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.682 ns" { avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|de2_tv2_0_avalon_master_0_arbiterlock~13 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1~198 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_data_master_qualified_request_sdram_0_s1 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~126 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~128 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|Add2~129 avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|cpu_0_instruction_master_granted_sdram_0_s1~66 avl_m_w:DUT|sdram_0:the_sdram_0|comb~12 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[38]~1162 avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27] } { 0.000ns 0.000ns 0.624ns 1.022ns 0.398ns 0.000ns 0.000ns 0.699ns 0.653ns 0.391ns 1.392ns } { 0.000ns 0.393ns 0.370ns 0.206ns 0.596ns 0.190ns 0.506ns 0.366ns 0.651ns 0.370ns 0.855ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}