📄 altsyncram_br41.tdf
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--altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="RESTRUCTURE" DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 WIDTHAD_B=10 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a
--VERSION_BEGIN 7.0 cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ VERSION_END
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION altsyncram_52f1 (aclr1, address_a[9..0], address_b[9..0], addressstall_a, clock0, clock1, clocken0, clocken1, data_a[15..0], data_b[15..0], wren_a, wren_b)
RETURNS ( q_a[15..0], q_b[15..0]);
--synthesis_resources = M4K 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_br41
(
aclr1 : input;
address_a[9..0] : input;
address_b[9..0] : input;
addressstall_b : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[15..0] : input;
q_b[15..0] : output;
wren_a : input;
)
VARIABLE
altsyncram3 : altsyncram_52f1;
BEGIN
altsyncram3.aclr1 = aclr1;
altsyncram3.address_a[] = address_b[];
altsyncram3.address_b[] = address_a[];
altsyncram3.addressstall_a = addressstall_b;
altsyncram3.clock0 = clock1;
altsyncram3.clock1 = clock0;
altsyncram3.clocken0 = clocken1;
altsyncram3.clocken1 = wren_a;
altsyncram3.data_a[] = B"1111111111111111";
altsyncram3.data_b[] = data_a[];
altsyncram3.wren_a = B"0";
altsyncram3.wren_b = wren_a;
q_b[] = altsyncram3.q_a[];
END;
--VALID FILE
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