dcfifo_8ef1.tdf

DE2_TV_m_write.rar是用来去处抖动的

--dcfifo CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=1024 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=10 LPM_WIDTHU_R=10 OVERFLOW_CHECKING="ON" RDSYNC_DELAYPIPE=4 UNDERFLOW_CHECKING="ON" USE_EAB="ON" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdempty rdreq wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="RESTRUCTURE" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 7.0 cbx_a_gray2bin 2006:02:28:14:37:30:SJ cbx_a_graycounter 2006:05:31:11:44:48:SJ cbx_altdpram 2006:11:03:15:22:16:SJ cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_dcfifo 2006:12:21:13:39:46:SJ cbx_fifo_common 2006:03:14:10:59:42:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_counter 2006:11:07:16:43:46:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_scfifo 2006:10:16:20:17:00:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


--  Copyright (C) 1991-2007 Altera Corporation
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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION a_gray2bin_ldb (gray[10..0])
RETURNS ( bin[10..0]);
FUNCTION a_graycounter_p96 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION a_graycounter_k27 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION a_graycounter_l27 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION altsyncram_br41 (aclr1, address_a[9..0], address_b[9..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION alt_synch_pipe_1e8 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION dffpipe_se9 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION alt_synch_pipe_2e8 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);

--synthesis_resources = lut 62 M4K 4 reg 115 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;{-to p0addr} POWER_UP_LEVEL=LOW;{-to rdaclr} suppress_da_rule_internal=c106;{-to rdaclr} POWER_UP_LEVEL=LOW;{ -from ""rdptr_g"" -to ""ws_dgrp|dffpipe9|dffe10a"" }CUT=ON;{ -from ""delayed_wrptr_g"" -to ""rs_dgwp|dffpipe5|dffe6a"" }CUT=ON";

SUBDESIGN dcfifo_8ef1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[9..0]	:	output;
) 
VARIABLE 
	wrptr_g_gray2bin : a_gray2bin_ldb;
	ws_dgrp_gray2bin : a_gray2bin_ldb;
	rdptr_g1p : a_graycounter_p96;
	wrptr_g1p : a_graycounter_k27;
	wrptr_gp : a_graycounter_l27;
	fifo_ram : altsyncram_br41;
	delayed_wrptr_g[10..0] : dffe;
	p0addr : dffe
		WITH (
			power_up = "low"
		);
	rdaclr : dffe
		WITH (
			power_up = "low"
		);
	rdptr_g[10..0] : dffe;
	rs_dgwp : alt_synch_pipe_1e8;
	ws_brp : dffpipe_se9;
	ws_bwp : dffpipe_se9;
	ws_dgrp : alt_synch_pipe_2e8;
	wrusedw_sub_dataa[10..0]	:	WIRE;
	wrusedw_sub_datab[10..0]	:	WIRE;
	wrusedw_sub_result[10..0]	:	WIRE;
	rdempty_eq_comp_aeb_int	:	WIRE;
	rdempty_eq_comp_aeb	:	WIRE;
	rdempty_eq_comp_dataa[10..0]	:	WIRE;
	rdempty_eq_comp_datab[10..0]	:	WIRE;
	wrfull_eq_comp_aeb_int	:	WIRE;
	wrfull_eq_comp_aeb	:	WIRE;
	wrfull_eq_comp_dataa[10..0]	:	WIRE;
	wrfull_eq_comp_datab[10..0]	:	WIRE;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	ram_address_a[9..0]	: WIRE;
	ram_address_b[9..0]	: WIRE;
	rdcnt_addr_ena	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;
	wrptr_gs[10..0]	: WIRE;

BEGIN 
	wrptr_g_gray2bin.gray[10..0] = wrptr_gp.q[10..0];
	ws_dgrp_gray2bin.gray[10..0] = ws_dgrp.q[10..0];
	rdptr_g1p.aclr = (! rdaclr.q);
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = rdcnt_addr_ena;
	wrptr_g1p.aclr = aclr;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	wrptr_gp.aclr = aclr;
	wrptr_gp.clock = wrclk;
	wrptr_gp.cnt_en = valid_wrreq;
	fifo_ram.aclr1 = aclr;
	fifo_ram.address_a[] = ram_address_a[];
	fifo_ram.address_b[] = ram_address_b[];
	fifo_ram.addressstall_b = (! rdcnt_addr_ena);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].clk = wrclk;
	delayed_wrptr_g[].clrn = (! aclr);
	delayed_wrptr_g[].d = wrptr_gp.q[];
	p0addr.clk = rdclk;
	p0addr.clrn = rdaclr.q;
	p0addr.d = B"1";
	rdaclr.clk = (! rdclk);
	rdaclr.clrn = (! aclr);
	rdaclr.d = B"1";
	rdptr_g[].clk = rdclk;
	rdptr_g[].clrn = (! aclr);
	rdptr_g[].d = rdptr_g1p.q[];
	rdptr_g[].ena = valid_rdreq;
	rs_dgwp.clock = rdclk;
	rs_dgwp.clrn = (! aclr);
	rs_dgwp.d[] = delayed_wrptr_g[].q;
	ws_brp.clock = wrclk;
	ws_brp.clrn = (! aclr);
	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
	ws_bwp.clock = wrclk;
	ws_bwp.clrn = (! aclr);
	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
	ws_dgrp.clock = wrclk;
	ws_dgrp.clrn = (! aclr);
	ws_dgrp.d[] = rdptr_g[].q;
	wrusedw_sub_result[] = wrusedw_sub_dataa[] - wrusedw_sub_datab[];
	wrusedw_sub_dataa[] = ws_bwp.q[];
	wrusedw_sub_datab[] = ws_brp.q[];
	IF (rdempty_eq_comp_dataa[] == rdempty_eq_comp_datab[]) THEN
		rdempty_eq_comp_aeb_int = VCC;
	ELSE
		rdempty_eq_comp_aeb_int = GND;
	END IF;
	rdempty_eq_comp_aeb = rdempty_eq_comp_aeb_int;
	rdempty_eq_comp_dataa[] = rs_dgwp.q[];
	rdempty_eq_comp_datab[] = rdptr_g[].q;
	IF (wrfull_eq_comp_dataa[] == wrfull_eq_comp_datab[]) THEN
		wrfull_eq_comp_aeb_int = VCC;
	ELSE
		wrfull_eq_comp_aeb_int = GND;
	END IF;
	wrfull_eq_comp_aeb = wrfull_eq_comp_aeb_int;
	wrfull_eq_comp_dataa[] = ws_dgrp.q[];
	wrfull_eq_comp_datab[] = wrptr_gs[];
	int_rdempty = rdempty_eq_comp_aeb;
	int_wrfull = wrfull_eq_comp_aeb;
	q[] = fifo_ram.q_b[];
	ram_address_a[] = ( (wrptr_gp.q[10..10] $ wrptr_gp.q[9..9]), wrptr_gp.q[8..0]);
	ram_address_b[] = ( (rdptr_g1p.q[10..10] $ rdptr_g1p.q[9..9]), rdptr_g1p.q[8..0]);
	rdcnt_addr_ena = (valid_rdreq # (! p0addr.q));
	rdempty = int_rdempty;
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrfull = int_wrfull;
	wrptr_gs[] = ( (! wrptr_gp.q[10..10]), (! wrptr_gp.q[9..9]), wrptr_gp.q[8..0]);
	wrusedw[9..0] = wrusedw_sub_result[9..0];
END;
--VALID FILE