de2_tv.hif

DE2_TV_m_write.rar是用来去处抖动的

Version 7.0 Build 33 02/05/2007 SJ Web Edition
11
871
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
I2C_AV_Config
# storage
db|DE2_TV.(1).cnf
db|DE2_TV.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_AV_Config.v
af127c3c4dbb977d760b72f866bcca
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
CLK_Freq
50000000
PARAMETER_SIGNED_DEC
DEF
I2C_Freq
20000
PARAMETER_SIGNED_DEC
DEF
LUT_SIZE
40
PARAMETER_SIGNED_DEC
DEF
SET_VIDEO
0
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1
}
# end
# entity
I2C_Controller
# storage
db|DE2_TV.(2).cnf
db|DE2_TV.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_Controller.v
f8e3f19243cbdb6ef4d39fe9182f8f3
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1|I2C_Controller:u0
}
# end
# entity
TD_Detect
# storage
db|DE2_TV.(3).cnf
db|DE2_TV.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
TD_Detect.v
243b2868c42c572cc8dece1f912c11b6
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2
}
# end
# entity
Reset_Delay
# storage
db|DE2_TV.(4).cnf
db|DE2_TV.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Reset_Delay.v
ea3ffecedd5b32c7b31b9256247493b6
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3
}
# end
# entity
ITU_656_Decoder
# storage
db|DE2_TV.(5).cnf
db|DE2_TV.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ITU_656_Decoder.v
896912cb251d8ce842f82ad4120d91a
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|ITU_656_Decoder:u4
}
# end
# entity
YUV422_to_444
# storage
db|DE2_TV.(6).cnf
db|DE2_TV.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
YUV422_to_444.v
b57449cd75a49b2366eb55cc6987d025
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YUV422_to_444:u5
}
# end
# entity
YCbCr2RGB
# storage
db|DE2_TV.(7).cnf
db|DE2_TV.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
YCbCr2RGB.v
cc7fad423f9edac658997389343a557
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6
}
# end
# entity
MAC_3
# storage
db|DE2_TV.(8).cnf
db|DE2_TV.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MAC_3.v
a4ea7726e7ca46f35de04b193e94
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2
}
# end
# entity
altmult_add
# storage
db|DE2_TV.(9).cnf
db|DE2_TV.(9).cnf
# case_insensitive
# source_file
c:|altera|70|quartus|libraries|megafunctions|altmult_add.tdf
5632254652da067486546c033b7e71
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_A1
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_A2
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_B1
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_B2
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR2
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
3
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR0
PARAMETER_UNKNOWN
USR
OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
SIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_SIGNED_DEC
USR
WIDTH_B
17
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
27
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_4f74
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
sourceb
-1
1
sourcea
-1
1
signb
-1
1
signa
-1
1
scaninb
-1
1
scanina
-1
1
mult23_saturation
-1
1
mult23_round
-1
1
mult01_saturation
-1
1
mult01_round
-1
1
addnsub3_round
-1
1
addnsub1_round
-1
1
aclr3
-1
1
aclr2
-1
1
aclr1
-1
1
ena3
-1
2
ena2
-1
2
ena1
-1
2
ena0
-1
2
clock3
-1
2
clock2
-1
2
clock1
-1
2
addnsub3
-1
2
addnsub1
-1
2
}
# include_file {
c:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
c:|altera|70|quartus|libraries|megafunctions|stratix_mac_out.inc
7e6e79cdf4a1237186d7c89ebab37e
c:|altera|70|quartus|libraries|megafunctions|stratix_mac_mult.inc
37fae19b7be3fd367b8beebe8242bb70
}
# hierarchies {
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1|altmult_add:ALTMULT_ADD_component
avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2|altmult_add:ALTMULT_ADD_component
}
# end
# entity
mult_add_4f74
# storage
db|DE2_TV.(10).cnf
db|DE2_TV.(10).cnf
# case_insensitive
# source_file
db|mult_add_4f74.tdf
6b22c8177348db5f41d7c2c7bfe260
6
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab50
-1
3
datab5
-1
3
datab49
-1
3