lpm_divide_d6t.tdf

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--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_PIPELINE=1 LPM_REMAINDERPOSITIVE="TRUE" LPM_WIDTHD=4 LPM_WIDTHN=10 OPTIMIZE_FOR_SPEED=5 aclr clken(vcc) clock denom numer quotient remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 6.1 cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


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--  functions, and any output files from any of the foregoing 
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FUNCTION sign_div_unsign_3li (aclr, clock, denominator[3..0], numerator[9..0])
RETURNS ( quotient[9..0], remainder[3..0]);

--synthesis_resources = lut 50 reg 29 
SUBDESIGN lpm_divide_d6t
( 
	aclr	:	input;
	clken	:	input;
	clock	:	input;
	denom[3..0]	:	input;
	numer[9..0]	:	input;
	quotient[9..0]	:	output;
	remain[3..0]	:	output;
) 
VARIABLE 
	divider : sign_div_unsign_3li;
	numer_tmp[9..0]	: WIRE;

BEGIN 
	divider.aclr = aclr;
	divider.clock = clock;
	divider.denominator[] = denom[];
	divider.numerator[] = numer_tmp[];
	numer_tmp[] = numer[];
	quotient[] = divider.quotient[];
	remain[] = divider.remainder[];
END;
--VALID FILE