de2_tv.fit.qmsg

DE2_TV_m_write.rar是用来去处抖动的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Web Edition " "Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 30 20:55:22 2008 " "Info: Processing started: Sun Mar 30 20:55:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_TV -c DE2_TV " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_TV -c DE2_TV" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_TV EP2C35F672C8 " "Info: Selected device EP2C35F672C8 for design \"DE2_TV\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_SET_COMPENSATE_CLK" "SDRAM_PLL:PLL1\|altpll:altpll_component\|pll clock1 " "Warning: Compensate clock of PLL \"SDRAM_PLL:PLL1\|altpll:altpll_component\|pll\" has been set to clock1" {  } { { "altpll.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "Compensate clock of PLL \"%1!s!\" has been set to %2!s!" 0 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"SDRAM_PLL:PLL1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}