⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 altsyncram_irg2.tdf

📁 DE2_TV_m_write.rar是用来去处抖动的
💻 TDF
📖 第 1 页 / 共 4 页
字号:
🔍
1234 
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a17 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a18 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a19 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a20 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a21 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a22 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 22,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a23 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a24 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a25 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "cpu_0_ociram_default_contents.mif",
			INIT_FILE_LAYOUT = "port_a",
			init_file_restructured = "./db/cpu_0_ociram_default_contents_mod.mif",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
1234

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -