📄 avl_m_w.v
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//synthesis translate_on
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module de2_tv2_0_avalon_master_0_arbitrator (
// inputs:
clk,
d1_sdram_0_s1_end_xfer,
de2_tv2_0_avalon_master_0_address,
de2_tv2_0_avalon_master_0_write,
de2_tv2_0_avalon_master_0_writedata,
de2_tv2_0_granted_sdram_0_s1,
de2_tv2_0_qualified_request_sdram_0_s1,
de2_tv2_0_requests_sdram_0_s1,
reset_n,
sdram_0_s1_waitrequest_from_sa,
// outputs:
de2_tv2_0_avalon_master_0_address_to_slave,
de2_tv2_0_avalon_master_0_waitrequest
)
/* synthesis auto_dissolve = "FALSE" */ ;
output [ 31: 0] de2_tv2_0_avalon_master_0_address_to_slave;
output de2_tv2_0_avalon_master_0_waitrequest;
input clk;
input d1_sdram_0_s1_end_xfer;
input [ 31: 0] de2_tv2_0_avalon_master_0_address;
input de2_tv2_0_avalon_master_0_write;
input [ 15: 0] de2_tv2_0_avalon_master_0_writedata;
input de2_tv2_0_granted_sdram_0_s1;
input de2_tv2_0_qualified_request_sdram_0_s1;
input de2_tv2_0_requests_sdram_0_s1;
input reset_n;
input sdram_0_s1_waitrequest_from_sa;
reg active_and_waiting_last_time;
reg [ 31: 0] de2_tv2_0_avalon_master_0_address_last_time;
wire [ 31: 0] de2_tv2_0_avalon_master_0_address_to_slave;
wire de2_tv2_0_avalon_master_0_run;
wire de2_tv2_0_avalon_master_0_waitrequest;
reg de2_tv2_0_avalon_master_0_write_last_time;
reg [ 15: 0] de2_tv2_0_avalon_master_0_writedata_last_time;
wire r_0;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (de2_tv2_0_qualified_request_sdram_0_s1 | ~de2_tv2_0_requests_sdram_0_s1) & (de2_tv2_0_granted_sdram_0_s1 | ~de2_tv2_0_qualified_request_sdram_0_s1) & ((~de2_tv2_0_qualified_request_sdram_0_s1 | ~de2_tv2_0_avalon_master_0_write | (1 & ~sdram_0_s1_waitrequest_from_sa & de2_tv2_0_avalon_master_0_write)));
//cascaded wait assignment, which is an e_assign
assign de2_tv2_0_avalon_master_0_run = r_0;
//optimize select-logic by passing only those address bits which matter.
assign de2_tv2_0_avalon_master_0_address_to_slave = {9'b0,
de2_tv2_0_avalon_master_0_address[22 : 0]};
//actual waitrequest port, which is an e_assign
assign de2_tv2_0_avalon_master_0_waitrequest = ~de2_tv2_0_avalon_master_0_run;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//de2_tv2_0_avalon_master_0_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
de2_tv2_0_avalon_master_0_address_last_time <= 0;
else if (1)
de2_tv2_0_avalon_master_0_address_last_time <= de2_tv2_0_avalon_master_0_address;
end
//de2_tv2_0/avalon_master_0 waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else if (1)
active_and_waiting_last_time <= de2_tv2_0_avalon_master_0_waitrequest & (de2_tv2_0_avalon_master_0_write);
end
//de2_tv2_0_avalon_master_0_address matches last port_name, which is an e_process
always @(active_and_waiting_last_time or de2_tv2_0_avalon_master_0_address or de2_tv2_0_avalon_master_0_address_last_time)
begin
if (active_and_waiting_last_time & (de2_tv2_0_avalon_master_0_address != de2_tv2_0_avalon_master_0_address_last_time))
begin
$write("%0d ns: de2_tv2_0_avalon_master_0_address did not heed wait!!!", $time);
$stop;
end
end
//de2_tv2_0_avalon_master_0_write check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
de2_tv2_0_avalon_master_0_write_last_time <= 0;
else if (1)
de2_tv2_0_avalon_master_0_write_last_time <= de2_tv2_0_avalon_master_0_write;
end
//de2_tv2_0_avalon_master_0_write matches last port_name, which is an e_process
always @(active_and_waiting_last_time or de2_tv2_0_avalon_master_0_write or de2_tv2_0_avalon_master_0_write_last_time)
begin
if (active_and_waiting_last_time & (de2_tv2_0_avalon_master_0_write != de2_tv2_0_avalon_master_0_write_last_time))
begin
$write("%0d ns: de2_tv2_0_avalon_master_0_write did not heed wait!!!", $time);
$stop;
end
end
//de2_tv2_0_avalon_master_0_writedata check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
de2_tv2_0_avalon_master_0_writedata_last_time <= 0;
else if (1)
de2_tv2_0_avalon_master_0_writedata_last_time <= de2_tv2_0_avalon_master_0_writedata;
end
//de2_tv2_0_avalon_master_0_writedata matches last port_name, which is an e_process
always @(active_and_waiting_last_time or de2_tv2_0_avalon_master_0_write or de2_tv2_0_avalon_master_0_writedata or de2_tv2_0_avalon_master_0_writedata_last_time)
begin
if (active_and_waiting_last_time & (de2_tv2_0_avalon_master_0_writedata != de2_tv2_0_avalon_master_0_writedata_last_time) & de2_tv2_0_avalon_master_0_write)
begin
$write("%0d ns: de2_tv2_0_avalon_master_0_writedata did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module avl_m_w_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (1)
data_out <= data_in_d1;
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_avalon_jtag_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
jtag_uart_0_avalon_jtag_slave_dataavailable,
jtag_uart_0_avalon_jtag_slave_irq,
jtag_uart_0_avalon_jtag_slave_readdata,
jtag_uart_0_avalon_jtag_slave_readyfordata,
jtag_uart_0_avalon_jtag_slave_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
jtag_uart_0_avalon_jtag_slave_address,
jtag_uart_0_avalon_jtag_slave_chipselect,
jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa,
jtag_uart_0_avalon_jtag_slave_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_read_n,
jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa,
jtag_uart_0_avalon_jtag_slave_reset_n,
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
jtag_uart_0_avalon_jtag_slave_write_n,
jtag_uart_0_avalon_jtag_slave_writedata
)
/* synthesis auto_dissolve = "FALSE" */ ;
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