de2_tv2.v

DE2_TV_m_write.rar是用来去处抖动的

module DE2_TV2
	(
		OSC_27,							
		OSC_50,
		reset_n,						
		EXT_CLOCK,						
		KEY,							
		TDI,  							
		TCK,  							
		TCS,  							
	    TDO,  							
		I2C_SDAT,						
		I2C_SCLK,
		TD_DATA,    					
		TD_HS,							
		TD_VS,							
		TD_RESET,
		m_waitrequest,
		m_address,
		m_write,
		m_writedata
	);

////////////////////////	Clock Input	 	////////////////////////
input			OSC_27;					//	27 MHz
input			OSC_50;					//	50 MHz
input			EXT_CLOCK;				//	External Clock
////////////////////////	Push Button		////////////////////////
input	[3:0]	KEY;					//	Button[3:0]
input           reset_n;
////////////////////////	I2C		////////////////////////////////
inout			I2C_SDAT;				//	I2C Data
output			I2C_SCLK;				//	I2C Clock
////////////////////	USB JTAG link	////////////////////////////
input  			TDI;					// CPLD -> FPGA (data in)
input  			TCK;					// CPLD -> FPGA (clk)
input  			TCS;					// CPLD -> FPGA (CS)
output 			TDO;					// FPGA -> CPLD (data out)
////////////////////	TV Devoder		////////////////////////////
input	[7:0]	TD_DATA;    			//	TV Decoder Data bus 8 bits
input			TD_HS;					//	TV Decoder H_SYNC
input			TD_VS;					//	TV Decoder V_SYNC
output			TD_RESET;				//	TV Decoder Reset

input           m_waitrequest;

output  [31:0]  m_address;
output          m_write;
output  [15:0]  m_writedata;
////////////////////////	RGB DATA	////////////////////////////////
wire  [9:0]   Red;
wire  [9:0]   Green;
wire  [9:0]   Blue;
///////////////////////    control  signal    /////////////////////////
wire Dval;
wire  Field;
wire    [15:0]  m_writedata;
wire            FIFOempty;
wire    [9:0]   wrusedw;
wire            rdreq;

parameter addr_register1=32'h00100500;
parameter idle=3'b001;
parameter odd_address=3'b010;
parameter even_address=3'b100;


reg     [31:0]  m_address;
reg             m_write;
reg             rdreq_en;
reg     [9:0]   len_cont;
reg     [2:0]   state,next_state;
reg             add1,addset,add2,addset2,lenset,lenadd;
reg     [9:0]   len;


assign          rdreq=(rdreq_en)?((!m_waitrequest)&&(m_write)):0;





always@(posedge OSC_50 or negedge reset_n)
if(reset_n==0)  state<=idle;
else            state<=next_state;


always@(state or m_address or rdreq or len)
case(state)
  idle: begin
           addset=1; 
           addset2=0;
           add1=0;
           add2=0;
           lenset=0;
           lenadd=0;
           if(rdreq==1) 
           next_state=odd_address;
           else next_state=idle;
        end
  
  odd_address: begin
                 if(rdreq==1)
                 begin
                   if((m_address-addr_register1)>613116)
                    begin
                      addset=0;
                      add1=0;
                      add2=0;
                      addset2=1;
                      lenset=1;
                      lenadd=0;
                      next_state<=even_address;
                    end
                   else if(len==639)
                   begin
                     addset=0;
                     add1=0;
                     add2=1;
                     addset2=0;
                     lenset=1;
                     lenadd=0;
                     next_state=odd_address;
                   end
                   else 
                   begin
                     addset=0; 
                     add1=1;
                     add2=0;
                     addset2=0;lenset=0;
                     lenadd=1;
                     next_state=odd_address;
                   end
                 end
                 else 
                 begin 
                   addset=0;
                    add1=0;
                    add2=0;
                    addset2=0;
                    lenset=0;
                    lenadd=0;
                   next_state<=odd_address;
                 end  
               end
  
  even_address: begin
                 if(rdreq==1)
                 begin
                   if((m_address-addr_register1)>614396)
                    begin
                      addset=1;
                      add1=0;
                      add2=0;
                      addset2=0;
                      lenset=1;
                     lenadd=0;
                      next_state<=odd_address;
                    end
                   else if(len==639)
                   begin
                     addset=0;
                     add1=0;
                     add2=1;
                     addset2=0;
                     lenset=1;
                     lenadd=0;
                     next_state=even_address;
                   end
                   else 
                   begin
                     addset=0; 
                     add1=1;
                     add2=0;
                     addset2=0;
                      lenset=0;
                     lenadd=1;
                     next_state=even_address;
                   end
                 end
                 else 
                 begin 
                   addset=0;
                    add1=0;
                    add2=0;
                     addset2=0;
                     lenset=0;
                     lenadd=0;
                   next_state<=even_address;
                 end  
               end

endcase

always@(posedge OSC_50 or negedge reset_n)
begin
    if(reset_n==0)
    begin 
      m_address=addr_register1;
      len=0; 
    end
    else
    begin
        if(addset==1) m_address=addr_register1;
        if(add2==1) m_address=m_address+1282;
        if(add1==1)   m_address=m_address+2;
        if(addset2==1) m_address=addr_register1+1280;
        if(lenset==1)  len=0;
        if(lenadd==1)  len=len+1;
    end
end


/*always@(negedge Dval or negedge reset_n)
begin
  if(reset_n==0) wrreq=0;
  else wrreq=1;
end*/

wire  [15:0]  RGB565;   
assign RGB565={Red[7:3],Green[7:2],Blue[7:3]};
 
always@(negedge OSC_50 or negedge reset_n)
begin
  if(reset_n==0)
  begin
      m_write<=0;
      rdreq_en<=0;
  end 
  else if(FIFOempty==0)           
  begin
      m_write<=1;
      rdreq_en<=1;
  end
  else
  begin
    m_write<=0;
      rdreq_en<=0;
  end
end

write_FIFO1 u7(
                  .aclr(~reset_n),
	              .data(RGB565),
	              .rdclk(OSC_50),
	              .rdreq(rdreq),
	              .wrclk(~OSC_27),
	              .wrreq(Dval),
	              .q(m_writedata),
	              .rdempty(FIFOempty),
	              .wrusedw(wrusedw) 
	          );

DE2_TV1 u9(
		.OSC_27(OSC_27),							
		.OSC_50(OSC_50),						
		.EXT_CLOCK(EXT_CLOCK),
                .KEY(KEY),													
		.TDI(TDI),  						
		.TCK(TCK),  						
		.TCS(TCS),  						
	        .TDO(TDO),  							
		.I2C_SDAT(I2C_SDAT),					
		.I2C_SCLK(I2C_SCLK),					
		.TD_DATA(TD_DATA),    				
		.TD_HS(TD_HS),						
		.TD_VS(TD_VS),							
		.TD_RESET(TD_RESET),						
	        .Red(Red),
		.Green(Green),
		.Blue(Blue),
		.DVAL(Dval),
		.Field(Field)					
	);
	endmodule