📄 class.ptf
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vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oAUD_DATA
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oAUD_LRCK
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iSrc_Select
{
width = "2";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iCLK_18_4
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iRST_N
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "AUDIO_DAC";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER ref_clk
{
parameter_name = "REF_CLK";
type = "integer";
default_value = "18432000";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sample_rate
{
parameter_name = "SAMPLE_RATE";
type = "integer";
default_value = "48000";
editable = "1";
tooltip = "";
}
HDL_PARAMETER data_width
{
parameter_name = "DATA_WIDTH";
type = "integer";
default_value = "16";
editable = "1";
tooltip = "";
}
HDL_PARAMETER channel_num
{
parameter_name = "CHANNEL_NUM";
type = "integer";
default_value = "2";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sin_sample_data
{
parameter_name = "SIN_SAMPLE_DATA";
type = "integer";
default_value = "48";
editable = "1";
tooltip = "";
}
HDL_PARAMETER flash_data_num
{
parameter_name = "FLASH_DATA_NUM";
type = "integer";
default_value = "1048576";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sdram_data_num
{
parameter_name = "SDRAM_DATA_NUM";
type = "integer";
default_value = "4194304";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sram_data_num
{
parameter_name = "SRAM_DATA_NUM";
type = "integer";
default_value = "262144";
editable = "1";
tooltip = "";
}
HDL_PARAMETER flash_addr_width
{
parameter_name = "FLASH_ADDR_WIDTH";
type = "integer";
default_value = "20";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sdram_addr_width
{
parameter_name = "SDRAM_ADDR_WIDTH";
type = "integer";
default_value = "22";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sram_addr_width
{
parameter_name = "SRAM_ADDR_WIDTH";
type = "integer";
default_value = "18";
editable = "1";
tooltip = "";
}
HDL_PARAMETER flash_data_width
{
parameter_name = "FLASH_DATA_WIDTH";
type = "integer";
default_value = "8";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sdram_data_width
{
parameter_name = "SDRAM_DATA_WIDTH";
type = "integer";
default_value = "16";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sram_data_width
{
parameter_name = "SRAM_DATA_WIDTH";
type = "integer";
default_value = "16";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sin_sanple
{
parameter_name = "SIN_SANPLE";
type = "integer";
default_value = "0";
editable = "1";
tooltip = "";
}
HDL_PARAMETER flash_data
{
parameter_name = "FLASH_DATA";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sdram_data
{
parameter_name = "SDRAM_DATA";
type = "integer";
default_value = "2";
editable = "1";
tooltip = "";
}
HDL_PARAMETER sram_data
{
parameter_name = "SRAM_DATA";
type = "integer";
default_value = "3";
editable = "1";
tooltip = "";
}
}
}
}
}
}
FILE DE2_TV1.v
{
file_mod = "Wed Mar 26 21:23:47 CST 2008";
quartus_map_start = "Thu Mar 27 12:43:39 CST 2008";
quartus_map_finished = "Thu Mar 27 12:43:51 CST 2008";
#found 1 valid modules
WRAPPER DE2_TV1
{
CLASS DE2_TV1
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "D:/DE2_TV_New_v1/DE2_TV1.v";
}
}
top_module_name = "DE2_TV1";
emit_system_h = "0";
}
MODULE_DEFAULTS global_signals
{
class = "DE2_TV1";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT OSC_27
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OSC_50
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT EXT_CLOCK
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT KEY
{
width = "4";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT TDI
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT TCK
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT TCS
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT TDO
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT I2C_SDAT
{
width = "1";
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