📄 class.ptf
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{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Group = "2";
Has_Clock = "0";
Address_Width = "32";
Data_Width = "16";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Is_Asynchronous = "0";
Has_IRQ = "0";
Irq_Scheme = "none";
Interrupt_Range = "";
Is_Readable = "0";
Is_Writable = "1";
Is_Big_Endian = "0";
Register_Outgoing_Signals = "0";
}
COMPONENT_BUILDER
{
AVM_SETTINGS
{
stream_reads = "0";
stream_writes = "0";
irq_width = "0";
irq_number_width = "0";
irq_scheme = "none";
Is_Asynchronous = "0";
Is_Big_Endian = "0";
}
}
PORT_WIRING
{
PORT m_waitrequest
{
width = "1";
width_expression = "";
direction = "input";
type = "waitrequest";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT m_address
{
width = "32";
width_expression = "";
direction = "output";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT m_write
{
width = "1";
width_expression = "";
direction = "output";
type = "write";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT m_writedata
{
width = "16";
width_expression = "";
direction = "output";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "DE2_TV2";
technology = "Unknown Group";
}
WIZARD_UI the_wizard_ui
{
title = "DE2_TV2 - {{ $MOD }}";
CONTEXT
{
H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
M = "";
SBI_global_signals = "SYSTEM_BUILDER_INFO";
SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
SBI_avalon_master_0 = "MASTER avalon_master_0/SYSTEM_BUILDER_INFO";
}
PAGES main
{
PAGE 1
{
align = "left";
title = "<b>DE2_TV2 1.0</b> Settings";
layout = "vertical";
TEXT
{
title = "Built on: 2008.03.30.20:42:35";
}
TEXT
{
title = "Class name: de2_tv2";
}
TEXT
{
title = "Class version: 1.0";
}
TEXT
{
title = "Component name: DE2_TV2";
}
TEXT
{
title = "Component Group: Unknown Group";
}
GROUP parameters
{
title = "Parameters";
layout = "form";
align = "left";
EDIT e1
{
id = "addr_register1";
editable = "1";
title = "addr_register1:";
columns = "40";
tooltip = "default value: 32'b00000000000100000000010100000000";
DATA
{
$H/addr_register1 = "$";
}
q = "'";
warning = "{{ if(!(regexp('ugly_'+$H/addr_register1,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/addr_register1,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/addr_register1,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/addr_register1,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/addr_register1,'ugly_-?[0-9]+')))'addr_register1 must be numeric constant, not '+$H/addr_register1; }}";
}
EDIT e2
{
id = "idle";
editable = "1";
title = "idle:";
columns = "40";
tooltip = "default value: 3'b001";
DATA
{
$H/idle = "$";
}
q = "'";
warning = "{{ if(!(regexp('ugly_'+$H/idle,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/idle,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/idle,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/idle,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/idle,'ugly_-?[0-9]+')))'idle must be numeric constant, not '+$H/idle; }}";
}
EDIT e3
{
id = "odd_address";
editable = "1";
title = "odd_address:";
columns = "40";
tooltip = "default value: 3'b010";
DATA
{
$H/odd_address = "$";
}
q = "'";
warning = "{{ if(!(regexp('ugly_'+$H/odd_address,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/odd_address,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/odd_address,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/odd_address,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/odd_address,'ugly_-?[0-9]+')))'odd_address must be numeric constant, not '+$H/odd_address; }}";
}
EDIT e4
{
id = "even_address";
editable = "1";
title = "even_address:";
columns = "40";
tooltip = "default value: 3'b100";
DATA
{
$H/even_address = "$";
}
q = "'";
warning = "{{ if(!(regexp('ugly_'+$H/even_address,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/even_address,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/even_address,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/even_address,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/even_address,'ugly_-?[0-9]+')))'even_address must be numeric constant, not '+$H/even_address; }}";
}
}
}
}
}
}
SOPC_Builder_Version = "7.00";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER addr_register1
{
parameter_name = "addr_register1";
type = "integer";
default_value = "32'b00000000000100000000010100000000";
editable = "1";
tooltip = "";
}
HDL_PARAMETER idle
{
parameter_name = "idle";
type = "integer";
default_value = "3'b001";
editable = "1";
tooltip = "";
}
HDL_PARAMETER odd_address
{
parameter_name = "odd_address";
type = "integer";
default_value = "3'b010";
editable = "1";
tooltip = "";
}
HDL_PARAMETER even_address
{
parameter_name = "even_address";
type = "integer";
default_value = "3'b100";
editable = "1";
tooltip = "";
}
}
SW_FILES
{
}
built_on = "2008.03.30.20:42:35";
CACHED_HDL_INFO
{
# cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
# used only by Component Builder
FILE AUDIO_DAC.v
{
file_mod = "Mon Aug 15 15:38:40 CST 2005";
quartus_map_start = "Thu Mar 27 12:43:32 CST 2008";
quartus_map_finished = "Thu Mar 27 12:43:39 CST 2008";
#found 1 valid modules
WRAPPER AUDIO_DAC
{
CLASS AUDIO_DAC
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "D:/DE2_TV_New_v1/AUDIO_DAC.v";
}
}
top_module_name = "AUDIO_DAC";
emit_system_h = "0";
}
MODULE_DEFAULTS global_signals
{
class = "AUDIO_DAC";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT oFLASH_ADDR
{
width = "-1";
width_expression = "(FLASH_ADDR_WIDTH-1) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iFLASH_DATA
{
width = "-1";
width_expression = "(FLASH_DATA_WIDTH-1) - (0) + 1";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oSDRAM_ADDR
{
width = "-1";
width_expression = "(SDRAM_ADDR_WIDTH) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iSDRAM_DATA
{
width = "-1";
width_expression = "(SDRAM_DATA_WIDTH-1) - (0) + 1";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oSRAM_ADDR
{
width = "-1";
width_expression = "(SRAM_ADDR_WIDTH) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iSRAM_DATA
{
width = "-1";
width_expression = "(SRAM_DATA_WIDTH-1) - (0) + 1";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oAUD_BCK
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
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