de2_tv.tan.summary

DE2_TV_m_write.rar是用来去处抖动的

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.835 ns
From           : TD_DATA[4]
To             : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|ITU_656_Decoder:u4|TV_Y[9]
From Clock     : --
To Clock       : OSC_27
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 3.152 ns
From           : avl_m_w:DUT|sdram_0:the_sdram_0|m_bank[0]
To             : DRAM_BA_0
From Clock     : OSC_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.343 ns
From           : KEY[0]
To             : TD_RESET
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.699 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'OSC_50'
Slack          : -13.444 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : avl_m_w:DUT|cpu_0:the_cpu_0|d_write
To             : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_address[31]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : OSC_50
Failed Paths   : 2770

Type           : Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : -2.697 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|m_write
To             : avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entry_1[27]
From Clock     : OSC_50
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 1389

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 62.52 MHz ( period = 15.996 ns )
From           : sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'OSC_27'
Slack          : N/A
Required Time  : None
Actual Time    : 105.84 MHz ( period = 9.448 ns )
From           : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|oDVAL
To             : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|a_graycounter_l27:wrptr_gp|counter_ffa[10]
From Clock     : OSC_27
To Clock       : OSC_27
Failed Paths   : 0

Type           : Clock Setup: 'TD_HS'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 360.10 MHz ( period = 2.777 ns )
From           : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2|Stable_Cont[0]
To             : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2|Stable_Cont[7]
From Clock     : TD_HS
To Clock       : TD_HS
Failed Paths   : 0

Type           : Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 0.499 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : avl_m_w:DUT|sdram_0:the_sdram_0|i_cmd[3]
To             : avl_m_w:DUT|sdram_0:the_sdram_0|i_cmd[3]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'OSC_50'
Slack          : 0.499 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_0
To             : avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3|oRST_0
From Clock     : OSC_50
To Clock       : OSC_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 4159

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