de2_tv2_0.v

DE2_TV_m_write.rar是用来去处抖动的

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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module de2_tv2_0 (
                   // inputs:
                    EXT_CLOCK,
                    KEY,
                    OSC_27,
                    OSC_50,
                    TCK,
                    TCS,
                    TDI,
                    TD_DATA,
                    TD_HS,
                    TD_VS,
                    m_waitrequest,
                    reset_n,

                   // outputs:
                    I2C_SCLK,
                    I2C_SDAT,
                    TDO,
                    TD_RESET,
                    m_address,
                    m_write,
                    m_writedata
                 )
;

  output           I2C_SCLK;
  inout            I2C_SDAT;
  output           TDO;
  output           TD_RESET;
  output  [ 31: 0] m_address;
  output           m_write;
  output  [ 15: 0] m_writedata;
  input            EXT_CLOCK;
  input   [  3: 0] KEY;
  input            OSC_27;
  input            OSC_50;
  input            TCK;
  input            TCS;
  input            TDI;
  input   [  7: 0] TD_DATA;
  input            TD_HS;
  input            TD_VS;
  input            m_waitrequest;
  input            reset_n;

  wire             I2C_SCLK;
  wire             I2C_SDAT;
  wire             TDO;
  wire             TD_RESET;
  wire    [ 31: 0] m_address;
  wire             m_write;
  wire    [ 15: 0] m_writedata;
  DE2_TV2 the_DE2_TV2
    (
      .EXT_CLOCK     (EXT_CLOCK),
      .I2C_SCLK      (I2C_SCLK),
      .I2C_SDAT      (I2C_SDAT),
      .KEY           (KEY),
      .OSC_27        (OSC_27),
      .OSC_50        (OSC_50),
      .TCK           (TCK),
      .TCS           (TCS),
      .TDI           (TDI),
      .TDO           (TDO),
      .TD_DATA       (TD_DATA),
      .TD_HS         (TD_HS),
      .TD_RESET      (TD_RESET),
      .TD_VS         (TD_VS),
      .m_address     (m_address),
      .m_waitrequest (m_waitrequest),
      .m_write       (m_write),
      .m_writedata   (m_writedata),
      .reset_n       (reset_n)
    );
  defparam the_DE2_TV2.addr_register1 = 32'b00000000000100000000010100000000,
           the_DE2_TV2.even_address = 3'b100,
           the_DE2_TV2.idle = 3'b001,
           the_DE2_TV2.odd_address = 3'b010;


endmodule