sdram_control.v

DE2_TV_m_write.rar是用来去处抖动的

module  sdram_control(  
		// Clock Input
		OSC_27,							
		OSC_50,						
		//Push Button		
		reset_n,
		EXT_CLOCK,						//	External Clock
	    ////////////////////	USB JTAG link	////////////////////
		TDI,  							// CPLD -> FPGA (data in)
		TCK,  							// CPLD -> FPGA (clk)
		TCS,  							// CPLD -> FPGA (CS)
	    TDO,  							// FPGA -> CPLD (data out)
		////////////////////	I2C		////////////////////////////
		I2C_SDAT,						//	I2C Data
		I2C_SCLK,						//	I2C Clock
		////////////////	TV Decoder		////////////////////////
		TD_DATA,    					//	TV Decoder Data bus 8 bits
		TD_HS,							//	TV Decoder H_SYNC
		TD_VS,							//	TV Decoder V_SYNC
		TD_RESET,						//	TV Decoder Reset							
		//Avalon port
		m_waitrequest,
		m_address,
		m_write,
		m_writedata                );

input           OSC_27;       				
input		    OSC_50;
input		    reset_n;
input			EXT_CLOCK;				//	External Clock


////////////////////////	I2C		////////////////////////////////
inout			I2C_SDAT;				//	I2C Data
output			I2C_SCLK;				//	I2C Clock
////////////////////	USB JTAG link	////////////////////////////
input  			TDI;					// CPLD -> FPGA (data in)
input  			TCK;					// CPLD -> FPGA (clk)
input  			TCS;					// CPLD -> FPGA (CS)
output 			TDO;					// FPGA -> CPLD (data out)
////////////////////	TV Devoder		////////////////////////////
input	[7:0]	TD_DATA;    			//	TV Decoder Data bus 8 bits
input			TD_HS;					//	TV Decoder H_SYNC
input			TD_VS;					//	TV Decoder V_SYNC
output			TD_RESET;				//	TV Decoder Reset
////////////////////	Avalon port/////////////////////////////////
input           m_waitrequest;
output  [31:0]  m_address;
output          m_write;
output  [15:0]  m_writedata;



reg     [31:0]  m_address;
reg             m_write;
reg     [31:0]  s_readdata;
reg     [31:0]  len_cont;
reg             next_m_write;
reg             wrreq;
reg             rdreq_en;
reg     [15:0]  count;
reg     [31:0]  p_address;
reg     [15:0]  count1;
reg     [1:0]   state,next_state;
reg     [1:0]   FIFO_state,next_FIFO_state;

wire    [15:0]  m_writedata;
wire            FIFOempty;
wire    [9:0]   wrusedw;
wire            rdreq;

assign          rdreq=(rdreq_en)?((!m_waitrequest)&&(m_write)):0;

parameter  addr_register1 = 32'h00100500;

//the follow is avalon master port
always@(posedge OSC_50 or negedge reset_n) //get length count 
begin 
   if(!reset_n)  len_cont=640;
   else if(len_cont==1)  len_cont=640;
   else if(rdreq)  len_cont=len_cont-1;
end



always@(negedge Dval or negedge reset_n)
begin
  if(reset_n==0) wrreq=0;
  else wrreq=1;
end

always@(negedge reset_n or posedge OSC_50)
begin
  if(reset_n==0)    m_address=0;
  else if(rdreq)
  begin
    //if(len_cont==1) m_address=0;else            
     m_address=m_address+2;
  end
end
wire  [15:0]  RGB565;   
assign RGB565={Red[7:3],Green[7:2],Blue[7:3]};
 
always@(negedge OSC_50 or negedge reset_n)
begin
  if(reset_n==0)
  begin
      m_write<=0;
      rdreq_en<=0;
  end 
  else if(FIFOempty==0)           
  begin
      m_write<=1;
      rdreq_en<=1;
  end
  else
  begin
    m_write<=0;
      rdreq_en<=0;
  end
end

wire			EXT_CLOCK;				
wire			I2C_SDAT;				
wire			I2C_SCLK;				
wire  			TDI;					
wire  			TCK;					
wire  			TCS;					
wire 			TDO;					
wire	[7:0]	TD_DATA;    			
wire			TD_HS;					
wire			TD_VS;
wire			TD_RESET;				
wire    [9:0]   Red;
wire    [9:0]   Green;
wire    [9:0]   Blue;
wire            Dval;
wire            Field;


write_FIFO1 u7(
                  .aclr(~reset_n),
	              .data(RGB565),
	              .rdclk(OSC_50),
	              .rdreq(rdreq),
	              .wrclk(~OSC_27),
	              .wrreq(wrreq),
	              .q(m_writedata),
	              .rdempty(FIFOempty),
	              .wrusedw(wrusedw) );
	
DE2_TV u9(
		.OSC_27(OSC_27),							
		.OSC_50(OSC_50),						
		.EXT_CLOCK(EXT_CLOCK),													
		.TDI(TDI),  						
		.TCK(TCK),  						
		.TCS(TCS),  						
	    .TDO(TDO),  							
		.I2C_SDAT(I2C_SDAT),					
		.I2C_SCLK(I2C_SCLK),					
		.TD_DATA(TD_DATA),    				
		.TD_HS(TD_HS),						
		.TD_VS(TD_VS),							
		.TD_RESET(TD_RESET),						
	    .Red(Red),
		.Green(Green),
		.Blue(Blue),
		.DVAL(Dval),
		.Field(Field)					
	);

endmodule