de2_tv.map.rpt

DE2_TV_m_write.rar是用来去处抖动的

; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+----------------------+--------------------------+
; Name                 ; Setting                  ;
+----------------------+--------------------------+
; CYCLONEII_SAFE_WRITE ; "RESTRUCTURE"            ;
+----------------------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                       ;
+-----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+
; File Name with User-Entered Path  ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                            ;
+-----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+
; DE2_TV2.v                         ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/DE2_TV2.v                                             ;
; write_FIFO1.v                     ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/write_FIFO1.v                                         ;
; DE2_TV1.v                         ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/DE2_TV1.v                                             ;
; MAC_3.v                           ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/MAC_3.v                                               ;
; Reset_Delay.v                     ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/Reset_Delay.v                                         ;
; YCbCr2RGB.v                       ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/YCbCr2RGB.v                                           ;
; DE2_TV.v                          ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/DE2_TV.v                                              ;
; I2C_AV_Config.v                   ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/I2C_AV_Config.v                                       ;
; I2C_Controller.v                  ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/I2C_Controller.v                                      ;
; YUV422_to_444.v                   ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/YUV422_to_444.v                                       ;
; TD_Detect.v                       ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/TD_Detect.v                                           ;
; ITU_656_Decoder.v                 ; yes             ; User Verilog HDL File        ; D:/DE2_TV_m_write/ITU_656_Decoder.v                                     ;
; SDRAM_PLL.v                       ; yes             ; Other                        ; D:/DE2_TV_m_write/SDRAM_PLL.v                                           ;
; altpll.tdf                        ; yes             ; Megafunction                 ; c:/altera/70/quartus/libraries/megafunctions/altpll.tdf                 ;
; aglobal70.inc                     ; yes             ; Megafunction                 ; c:/altera/70/quartus/libraries/megafunctions/aglobal70.inc              ;
; stratix_pll.inc                   ; yes             ; Megafunction                 ; c:/altera/70/quartus/libraries/megafunctions/stratix_pll.inc            ;
; stratixii_pll.inc                 ; yes             ; Megafunction                 ; c:/altera/70/quartus/libraries/megafunctions/stratixii_pll.inc          ;
; cycloneii_pll.inc                 ; yes             ; Megafunction                 ; c:/altera/70/quartus/libraries/megafunctions/cycloneii_pll.inc          ;
; system_Reset.v                    ; yes             ; Other                        ; D:/DE2_TV_m_write/system_Reset.v                                        ;
; avl_m_w.v                         ; yes             ; Other                        ; D:/DE2_TV_m_write/avl_m_w.v                                             ;
; cpu_0.v                           ; yes             ; Other                        ; D:/DE2_TV_m_write/cpu_0.v                                               ;
; cpu_0_test_bench.v                ; yes             ; Other                        ; D:/DE2_TV_m_write/cpu_0_test_bench.v                                    ;
; altsyncram.tdf                    ; yes             ; Megafunction                 ; c:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf             ;