📄 de2_tv.map.rpt
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80. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
81. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
82. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
83. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
84. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag
85. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram
86. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data
87. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram
88. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1
89. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2
90. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
91. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
92. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
93. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
94. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
95. Parameter Settings for User Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2
96. Parameter Settings for User Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component
97. Parameter Settings for User Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1
98. Parameter Settings for User Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component
99. Parameter Settings for User Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1|altmult_add:ALTMULT_ADD_component
100. Parameter Settings for User Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2|altmult_add:ALTMULT_ADD_component
101. Parameter Settings for User Entity Instance: avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
102. Parameter Settings for User Entity Instance: avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
103. Parameter Settings for User Entity Instance: avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
104. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
105. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
106. Parameter Settings for Inferred Entity Instance: avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1|altsyncram:WideOr0_rtl_0
107. altmult_add Parameter Settings by Entity Instance
108. dcfifo Parameter Settings by Entity Instance
109. scfifo Parameter Settings by Entity Instance
110. SignalTap II Logic Analyzer Settings
111. Analysis & Synthesis Messages
112. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Mar 30 20:55:12 2008 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Web Edition ;
; Revision Name ; DE2_TV ;
; Top-level Entity Name ; DE2_TV ;
; Family ; Cyclone II ;
; Total logic elements ; 3,735 ;
; Total combinational functions ; 3,735 ;
; Dedicated logic registers ; 3,214 ;
; Total registers ; 3214 ;
; Total pins ; 66 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 386,048 ;
; Embedded Multiplier 9-bit elements ; 22 ;
; Total PLLs ; 1 ;
+------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C8 ; ;
; Top-level entity name ; DE2_TV ; DE2_TV ;
; Family name ; Cyclone II ; Stratix ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
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