de2_tv.map.rpt

DE2_TV_m_write.rar是用来去处抖动的

Analysis & Synthesis report for DE2_TV
Sun Mar 30 20:55:13 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis DSP Block Usage Summary
 10. State Machine - |DE2_TV|avl_m_w:DUT|sdram_0:the_sdram_0|i_state
 11. State Machine - |DE2_TV|avl_m_w:DUT|sdram_0:the_sdram_0|i_next
 12. State Machine - |DE2_TV|avl_m_w:DUT|sdram_0:the_sdram_0|m_state
 13. State Machine - |DE2_TV|avl_m_w:DUT|sdram_0:the_sdram_0|m_next
 14. State Machine - |DE2_TV|avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|state
 15. State Machine - |DE2_TV|avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1|mSetup_ST
 16. State Machine - |DE2_TV|avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize
 17. Registers Protected by Synthesis
 18. Logic Cells Representing Combinational Loops
 19. Registers Removed During Synthesis
 20. General Register Statistics
 21. Inverted Register Statistics
 22. Multiplexer Restructuring Statistics (Restructuring Performed)
 23. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sbf1:auto_generated
 24. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sbf1:auto_generated|altsyncram_k1l1:altsyncram1
 25. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_d2i1:auto_generated
 26. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_amh1:auto_generated
 27. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_amh1:auto_generated|altsyncram_pfn1:altsyncram1
 28. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_koh1:auto_generated
 29. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_loh1:auto_generated
 30. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_ft52:auto_generated
 31. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_ft52:auto_generated|altsyncram_ckb2:altsyncram1
 32. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_qh52:auto_generated
 33. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_qh52:auto_generated|altsyncram_a682:altsyncram1
 34. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 35. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 36. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_sia2:auto_generated
 37. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_sia2:auto_generated|altsyncram_irg2:altsyncram1
 38. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_ui32:auto_generated
 39. Source assignments for avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_ui32:auto_generated|altsyncram_6c32:altsyncram1
 40. Source assignments for avl_m_w:DUT|avl_m_w_reset_clk_domain_synch_module:avl_m_w_reset_clk_domain_synch
 41. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component
 42. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated
 43. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|altsyncram_br41:fifo_ram
 44. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|altsyncram_br41:fifo_ram|altsyncram_52f1:altsyncram3
 45. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_1e8:rs_dgwp
 46. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_1e8:rs_dgwp|dffpipe_re9:dffpipe5
 47. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|dffpipe_se9:ws_brp
 48. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|dffpipe_se9:ws_bwp
 49. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_2e8:ws_dgrp
 50. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_2e8:ws_dgrp|dffpipe_te9:dffpipe9
 51. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated
 52. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1|dffpipe_b3c:pre_result
 53. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult2|dffpipe_b3c:pre_result
 54. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult3|dffpipe_b3c:pre_result
 55. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated
 56. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1|dffpipe_b3c:pre_result
 57. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult2|dffpipe_b3c:pre_result
 58. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u1|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult3|dffpipe_b3c:pre_result
 59. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated
 60. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1|dffpipe_b3c:pre_result
 61. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult2|dffpipe_b3c:pre_result
 62. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u2|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult3|dffpipe_b3c:pre_result
 63. Source assignments for avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|dpram_lu51:FIFOram|altsyncram_pap1:altsyncram2
 64. Source assignments for avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|dpram_lu51:FIFOram|altsyncram_pap1:altsyncram2
 65. Source assignments for avl_m_w:DUT|sdram_0:the_sdram_0
 66. Source assignments for sld_signaltap:auto_signaltap_0
 67. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_rbm2:auto_generated
 68. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_rbm2:auto_generated|altsyncram_m4l1:altsyncram1
 69. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 70. Source assignments for sld_hub:sld_hub_inst
 71. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 72. Source assignments for avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1|altsyncram:WideOr0_rtl_0|altsyncram_kn21:auto_generated
 73. Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component
 74. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
 75. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
 76. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
 77. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
 78. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
 79. Parameter Settings for User Entity Instance: avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram