de2_tv.map.smsg

DE2_TV_m_write.rar是用来去处抖动的

Info: Elaborating entity "altsyncram_br41" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|altsyncram_br41:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_52f1.tdf
    Info: Found entity 1: altsyncram_52f1
Info: Elaborating entity "altsyncram_52f1" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|altsyncram_br41:fifo_ram|altsyncram_52f1:altsyncram3"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1e8.tdf
    Info: Found entity 1: alt_synch_pipe_1e8
Info: Elaborating entity "alt_synch_pipe_1e8" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_1e8:rs_dgwp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf
    Info: Found entity 1: dffpipe_re9
Info: Elaborating entity "dffpipe_re9" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_1e8:rs_dgwp|dffpipe_re9:dffpipe5"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf
    Info: Found entity 1: dffpipe_se9
Info: Elaborating entity "dffpipe_se9" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|dffpipe_se9:ws_brp"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_2e8.tdf
    Info: Found entity 1: alt_synch_pipe_2e8
Info: Elaborating entity "alt_synch_pipe_2e8" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_2e8:ws_dgrp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_te9.tdf
    Info: Found entity 1: dffpipe_te9
Info: Elaborating entity "dffpipe_te9" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|write_FIFO1:u7|dcfifo:dcfifo_component|dcfifo_8ef1:auto_generated|alt_synch_pipe_2e8:ws_dgrp|dffpipe_te9:dffpipe9"
Info: Elaborating entity "DE2_TV1" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1"
Info: Elaborating entity "I2C_Controller" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|I2C_AV_Config:u1|I2C_Controller:u0"
Info: Elaborating entity "TD_Detect" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|TD_Detect:u2"
Info: Elaborating entity "Reset_Delay" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|Reset_Delay:u3"
Info: Elaborating entity "ITU_656_Decoder" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|ITU_656_Decoder:u4"
Info: Elaborating entity "YUV422_to_444" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YUV422_to_444:u5"
Info: Elaborating entity "YCbCr2RGB" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6"
Info: Elaborating entity "MAC_3" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0"
Info: Elaborating entity "altmult_add" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component"
Info: Elaborated megafunction instantiation "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_4f74.tdf
    Info: Found entity 1: mult_add_4f74
Info: Elaborating entity "mult_add_4f74" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_ob91.tdf
    Info: Found entity 1: ded_mult_ob91
Info: Elaborating entity "ded_mult_ob91" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_b3c.tdf
    Info: Found entity 1: dffpipe_b3c
Info: Elaborating entity "dffpipe_b3c" for hierarchy "avl_m_w:DUT|de2_tv2_0:the_de2_tv2_0|DE2_TV2:the_DE2_TV2|DE2_TV1:u9|YCbCr2RGB:u6|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1|dffpipe_b3c:pre_result"
Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_arbitrator" for hierarchy "avl_m_w:DUT|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"
Warning: Using design file jtag_uart_0.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: jtag_uart_0_log_module
    Info: Found entity 2: jtag_uart_0_sim_scfifo_w
    Info: Found entity 3: jtag_uart_0_scfifo_w
    Info: Found entity 4: jtag_uart_0_drom_module
    Info: Found entity 5: jtag_uart_0_sim_scfifo_r
    Info: Found entity 6: jtag_uart_0_scfifo_r
    Info: Found entity 7: jtag_uart_0
Info: Elaborating entity "jtag_uart_0" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0"
Info: Elaborating entity "jtag_uart_0_scfifo_w" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_h461.tdf
    Info: Found entity 1: scfifo_h461
Info: Elaborating entity "scfifo_h461" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_oa61.tdf
    Info: Found entity 1: a_dpfifo_oa61
Info: Elaborating entity "a_dpfifo_oa61" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_rj7.tdf
    Info: Found entity 1: cntr_rj7
Info: Elaborating entity "cntr_rj7" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_lu51.tdf
    Info: Found entity 1: dpram_lu51
Info: Elaborating entity "dpram_lu51" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|dpram_lu51:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pap1.tdf
    Info: Found entity 1: altsyncram_pap1
Info: Elaborating entity "altsyncram_pap1" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|dpram_lu51:FIFOram|altsyncram_pap1:altsyncram2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_fjb.tdf
    Info: Found entity 1: cntr_fjb
Info: Elaborating entity "cntr_fjb" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_h461:auto_generated|a_dpfifo_oa61:dpfifo|cntr_fjb:rd_ptr_count"
Info: Elaborating entity "jtag_uart_0_scfifo_r" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/alt_jtag_atlantic.v
    Info: Found entity 1: alt_jtag_atlantic
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "avl_m_w:DUT|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborating entity "sdram_0_s1_arbitrator" for hierarchy "avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module" for hierarchy "avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module" for hierarchy "avl_m_w:DUT|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1"
Warning: Using design file sdram_0.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: sdram_0_input_efifo_module
    Info: Found entity 2: sdram_0
Info: Elaborating entity "sdram_0" for hierarchy "avl_m_w:DUT|sdram_0:the_sdram_0"
Warning (10766): Verilog HDL warning at sdram_0.v(352): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "sdram_0_input_efifo_module" for hierarchy "avl_m_w:DUT|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"
Warning (10766): Verilog HDL warning at sdram_0.v(67): ignoring full_case attribute on case statement with explicit default
Warning (10766): Verilog HDL warning at sdram_0.v(93): ignoring full_case attribute on case statement with explicit default
Warning (10766): Verilog HDL warning at sdram_0.v(129): ignoring full_case attribute on case statement with explicit default
Warning: Port "iX" on the entity instantiation of "u5" is connected to a signal of width 1. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "address_b" on the entity instantiation of "cpu_0_traceram_lpm_dram_bdp_component" is connected to a signal of width 17. The formal width of the signal in the module is 7.  Extra bits will be ignored.
Warning: Port "jdo" on the entity instantiation of "the_cpu_0_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16.  Extra bits will be ignored.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit3_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit1_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored.
Info: Found 3 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap-rtl
    Info: Found entity 1: sld_signaltap
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Found 14 design units, including 7 entities, in source file c:/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_level_seq_mgr-rtl
    Info: Found design unit 3: sld_ela_state_machine-rtl
    Info: Found design unit 4: sld_ela_seg_state_machine-rtl
    Info: Found design unit 5: sld_ela_post_trigger_counter-rtl
    Info: Found design unit 6: sld_ela_segment_mgr-rtl
    Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl
    Info: Found entity 1: sld_ela_control
    Info: Found entity 2: sld_ela_level_seq_mgr
    Info: Found entity 3: sld_ela_state_machine
    Info: Found entity 4: sld_ela_seg_state_machine
    Info: Found entity 5: sld_ela_post_trigger_counter
    Info: Found entity 6: sld_ela_segment_mgr
    Info: Found entity 7: sld_ela_basic_multi_level_trigger
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "671116800"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "7"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "4096"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "12"