eeprom_interface.v

AT24C02的应用例程

// i2c.vhd
//
// This file implements an I2C Master interface that will read data
// from an external NVM (AT24C02A) at power-up to initialize a 256x8
// internal SRAM block. When external logic regs for an NVM write
// access, the block reads data from the external source and writes
// it to the specified I2C address.
//----------------------------------------------------------------------
//
//               Copyright 2004 Actel corporation
//
//----------------------------------------------------------------------
//
// Version 1.2  06/04/04 J.Vorgert - working file
//
//----------------------------------------------------------------------

`timescale 1ns / 1ps

module i2c (Reset_n, CLK, INIT, IENB, IADDR, IDATA, ICLK, UPDT,
            UENB, UADDR, UDATA, SDI, SDO, SCK);

input Reset_n;  /* active low reset */
input CLK    ;  /* processor clock  */
output INIT   ;  /* high during init */
output IENB   ;  /* low to enable write */
output [7:0] IADDR  ;  /* init address */
output [7:0] IDATA  ;  /* init data */
output ICLK   ;  /* init clock */

input UPDT   ;  /* high to trigger mirror image update */
output UENB   ;  /* low to enable fifo */
input [7:0] UADDR; /* write address */
input [7:0] UDATA;  /* write data */

input SDI    ;  /* serial input */
output SDO    ; /* active low open-drain drive enable - data */
output SCK    ; /* active low open-drain drive enable - clock */

reg IENB;
reg INIT;
reg UENB;
reg BTCK;
wire STEN;     
reg  [3:0] CSTATE;   
reg  [3:0] BCNT  ;  
reg  [7:0] CCNT  ;  
reg DLY     ;
reg D2 ;
wire D2I;
wire NKI     ;
reg NACK    ;
wire WRI     ;
wire RDI     ;
reg [8:0] BYTE   ; 
reg [8:0] SDATA  ; 
wire LD_BYTE  ;
reg STSP     ;
wire CTL_VAL  ;

always @ (posedge CLK or negedge Reset_n)
begin
  if(Reset_n == 1'b0) 
     BTCK <= 1'b0;
  else 
     BTCK <= #1 !BTCK;

end

// INIT is set at power-up and cleared when the state machine
// reaches state 0101.

always @ (negedge Reset_n or posedge CLK)
begin
  if(Reset_n == 1'b0) 
     INIT <= 1'b1;
  else if(CSTATE == 4'b0101)
        INIT <= #1 1'b0 ;
end 

// This state machine is set-up to read/write data to an AT24C02A 
// serial Flash memory
//
// At power-up, the INIT bit is set, and the state machine executes
// a 'sequencial read' operation starting at address 0x000 and 
// procedding until all 256 bytes have been read and forwarded into 
// the internal memory block. The state machine then sends a
// stop bit to the Flash and clears the INIT control bit.
//
// The state machine then waits for updt to be set.
// When the updt bit is set, the interface asserts u_enb low on a
// falling-edge of clk and addr/data is latched  on the next falling edge
// (rd_clk should be on the rising-edge).  The state machine writes
// data to the external FLASH memory one byte at a time whenever
// updt is asserted high.  If the FIFO remains 'not empty' then this
// block will poll the NVM until it is ready, and then proceed with
// a write cycle for the next byte.
//
// State Machine:
//
// 0000 - reset state:   generate a start bit and load 0xA0 command
// 0001 - send byte:     then load 0x00 address
// 0010 - send byte:     generate a start bit and load 0xA1 command
// 0011 - send byte:     clear byte count
// 0100 - receive byte:  if cnt /= FF: ack, cnt++, goto 0004 else: nack
// 0101 - stop:          assert stop bit and loop until updt = 1 - then
//                       generate a start bit and load A0
// 0110 - send byte:     send byte - if nack - goto 0101, else load Address
// 0111 - send byte:     send data byte, load data
// 1000 - send byte:     goto 0101
//
// In practice, the state machine is just a counter that starts at zero
// and counts up, then jumps back to 101 and counts up again,
// returning to zero only when reset_n is asserted low.

assign STEN = ( BCNT[3] == 1'b1 &&
                  (CSTATE[2] != 1'b1 || CSTATE[2:1] == 2'b11 ||
                   CSTATE[3]  == 1'b1 || (CSTATE == 4'b0100 && CCNT == 8'b11111111) ||
                  (CSTATE == 4'b0101 && UPDT == 1'b1)))?1'b1:1'b0;

always @(negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0)  
     CSTATE <= 4'b0000;
  else 
  begin
  if(STEN == 1'b1 && BTCK == 1'b0) 
        begin 
         if(CSTATE < 4'b0101 && NACK == 1'b1)
           CSTATE <= #1 4'b0000 ;
        end
   else 
        begin
        if (CSTATE[3] == 1'b1 || NACK == 1'b1)
          CSTATE <= #1 4'b0101 ;
        else
          CSTATE <= #1 CSTATE + 1'b1 ;
        end
  end
end

// The bit counter (BCNT) is cleared at the state transition
// and during the first cycle of state "0011" (for start bit).
// incremented on the falling-edge of clk when BTCK is low.

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0) 
     begin
     BCNT <= 4'b0000;
     DLY  <= 1'b0;
     end
  else
    begin
     if(BTCK == 1'b0)
       begin
       if(BCNT[3] == 1'b1 && CSTATE == 4'b0010) 
          DLY <= #1 1'b1;
       else
          DLY <= 1'b0;
       
       if(BCNT[3] == 1'b1 || (CSTATE == 4'b0011 && DLY == 1'b1)) 
          BCNT <= #1 4'b0000;
       else
          BCNT <= #1 BCNT + 1'b1;
       end
    
    end
end

// The byte counter (CCNT) is cleared in state 0011.
// It is incremented during the ACK bit after each
// byte transfer in state 0100 to count 0x00-0xFF bytes
// as they are read from the NVM.  ccnt is used both as
// a control signal and as the iaddr output.

assign D2I = (BTCK == 1'b1 && BCNT[3] == 1'b1 && CSTATE == 4'b0100)?1'b1:1'b0;
           

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0)
   begin
     CCNT <= 8'b0;
     D2   <= 1'b0;
   end
  else 
   begin
     D2 <= #1 D2I;
     if(CSTATE == 4'b0011) 
        CCNT <= #1 8'b0;
     else if(D2 == 1'b1)
        CCNT <= #1 CCNT + 1'b1;
     end
end

// the following logic checks the ACK bit for all states except
// states "0100" and "0101" and asserts NACK if the data pin is
// high during the 9th bit of any transfer.  This is registered 
// so that the value is present during state changes.


assign NKI = (BCNT[3] == 1'b1 && CSTATE != 4'b0100 && CSTATE != 4'b0101 && SDI == 1'b1)?1'b1:1'b0;

always @ (negedge Reset_n or posedge CLK)
begin
  if(Reset_n == 1'b0)
     NACK <= 1'b0;
  else if(BTCK == 1'b1)
     NACK <= #1 NKI;
end

// Write enables are cleared to 1 at power-up and are asserted low during
// ACK in state 0100.


assign WRI = (CSTATE == 4'b0100 && BCNT[3] == 1'b1 && BTCK == 1'b1)?1'b0:1'b1;

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0)
     IENB <= 1'b1;
  else
     IENB <= #1 WRI;
end

assign IADDR = CCNT[7:0];   /* use byte count as address */
assign IDATA = SDATA[8:1];  /* account for ACK bit */
assign ICLK = !BTCK;           /* invert BTCK and use the rising-edge of this signal as */
                             /*the write clock into internal SRAM */

// UENB is cleared to 1 at power-up and is asserted low in state 0111
// while BCNT=7 and BTCK=1.  It is clocked on the falling-edge
// of CLK so RD_CLK should occur on the rising-edge.

assign RDI = (CSTATE == 4'b0111 && BCNT == 4'b0111  && BTCK == 1'b1)?0:1;

always @ ( negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0) 
     UENB  <= 1'b1;
  else 
     UENB <= #1 RDI;
  
end

// The value that gets loaded into sdata is determined
// by which state we're exiting...

always @ (CSTATE or UDATA or UADDR)
begin
  case (CSTATE)
    4'b0000 :  BYTE = 9'b101000001; /* A0 */
    4'b0010 :  BYTE = 9'b101000011; /* A1 */
    4'b0101 :  BYTE = 9'b101000001; /* A0 */
    4'b0110 :  BYTE = {UADDR,1'b1};
    4'b0111 :  BYTE = {UDATA,1'b1};
    default :  BYTE = 9'b000000001; /* 0001,0011 */
  endcase
end

// The data register is 9 bits long (BYTE and ACK bit)
// It is parallel loaded during the ACK cycle in states
// 0000, 0001, 0010, 0011, 0101, 0110, and 0111;

assign LD_BYTE = (BCNT[3] == 1'b1 && BTCK == 1'b0 && CSTATE != 4'b0100 && CSTATE[3] == 1'b0)?1'b1:1'b0;

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0) 
     SDATA <= 9'b111111111;
  else 
     begin
     if(LD_BYTE == 1'b1) 
        SDATA <= #1 BYTE;
     else if((CSTATE != 4'b0101 && CSTATE != 4'b0100 && BTCK == 1'b0 && DLY == 1'b0) || 
           (CSTATE == 4'b0100 && BTCK == 1'b1)) 
            SDATA <= #1 {SDATA[7:0],SDI};
     end
end


// Start bits (data falling while BTCK is high) are generated as
// we exit states 0000, 0010, and 0101; stop bits (data rising
// while BTCK is high) are generated as we enter state 0101.
// This is done with the STSP signal.

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0) 
     STSP  <= 1'b1;
  else 
    begin
     if(((CSTATE == 4'b0000 || CSTATE == 4'b0101) && STEN == 1'b1 && BTCK == 1'b1) || (CSTATE == 4'b0011))
        STSP <= #1 1'b0;
     else if((CSTATE == 4'b0101 && BCNT == 4'b0000 && BTCK == 1'b1) ||
           (CSTATE == 4'b0010 && BCNT[3] == 1'b1)) 
        STSP <= #1 1'b1;
     
    end
end

// The serial output is driven either by stsp when
// outen is low, or by the MSBit of the shift register
// when oten is high.

assign CTL_VAL = (STSP == 1'b1 || (CSTATE == 4'b0100 && (BCNT[3] != 1'b1 || CCNT == 8'b11111111)))?1'b1:1'b0;

assign SDO = (CSTATE == 4'b0000 || DLY == 1'b1 || CSTATE == 4'b0100 || CSTATE == 4'b0101)?CTL_VAL:SDATA[8];

assign SCK = (BTCK == 1'b1 || (STSP == 1'b1 && (CSTATE == 4'b0000 || CSTATE == 4'b0101)))?1'b1:1'b0;

             
endmodule