i2c_tb.vhd

AT24C02的应用例程

-- i2C_tb.vhd
--
-- This file instanciates the I2C master, gives it a reset and clk and 
-- lets it run - then asserts p_updt and m_updt and runs some more...

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity i2c_tb is
port(dummy : out   std_logic := '0'   -- serial clock output
);   
end i2c_tb;

architecture testbench of i2c_tb is

component i2c is
port(reset_n  : in    std_logic;                     -- active low reset
     clk      : in    std_logic;                     -- processor clock

     init     : out   std_logic;                     -- high during init
     ienb     : out   std_logic;                     -- low to enable write
     iaddr    : out   std_logic_vector( 7 downto 0); -- init address
     idata    : out   std_logic_vector( 7 downto 0); -- init data
     iclk     : out   std_logic;                     -- init clock

     updt     : in    std_logic;  -- high to trigger mirror image update
     uenb     : out   std_logic;                     -- low to enable fifo
     uaddr    : in    std_logic_vector(7 downto 0);  -- write address
     udata    : in    std_logic_vector(7 downto 0);  -- write data

     sdi      : in    std_logic;  -- serial input 
     sdo      : out   std_logic;  -- active low open-drain drive enable - data
     sck      : out   std_logic   -- active low open-drain drive enable - clock
);   
end component;

component at24c02a is
port(reset_n : in    std_logic; -- active low reset (for simulation)
     sclk    : in    std_logic; -- serial data clock
     sdata   : inout std_logic; -- serial data
     A       : in    std_logic_vector(2 downto 0);
     wp      : in    std_logic
);   
end component;

signal reset_n : std_logic := '0';
signal clk     : std_logic := '0';
signal updt    : std_logic := '0';
signal sdi     : std_logic;
signal sdo     : std_logic;
signal sck     : std_logic;
signal sdata   : std_logic;

begin


reset_n <= '1' after 100 ns;
clk     <= NOT(clk) after 10 ns;

Process
begin
  updt <= '0';
  wait for 500 us;
  updt <= '1';      -- tell it to write bytes.
  wait for 10 us;
  updt <= '0';      -- now sit idle.
end process;

sdi <= '0' when (sdata = '0') else '1';
sdata <= '0' when (sdo = '0') else 'H';

PROM: at24c02a
port map(
     reset_n => reset_n,
     sclk    => sck,
     sdata   => sdata,
     A       => "000",
     wp      => '0'
);

uut: i2c
port map (
     reset_n  => reset_n,
     clk      => clk,

     init     => open,
     ienb     => open,
     iaddr    => open,
     idata    => open,
     iclk     => open,

     updt     => updt,
     uenb     => open,
     
     uaddr    => "10100101", -- A5
     udata    => "11000011", -- C3

     sdi      => sdi,
     sdo      => sdo,
     sck      => sck
);   

end testbench;