📄 main.lst
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1 000000 ;Note: Receive RF information sucess!
2 000000 ;add music
3 000000 ;*****************************************************************************
4 000000 ; 000000 00000 0000 0000 00000 0000 0000 *
5 000000 ; 00 00 00 00 0000 00 0 0 000 000 *
6 000000 ; 00 000 00 00 00 00 00 0 0 00 00 *
7 000000 ; 00 00 00 00 00 00 0 0 00 00 *
8 000000 ; 000000 00 00 00 00 00 0 0 000 *
9 000000 ; 000 00 00 00 00 00 00 0 0 00 00 *
10 000000 ; 00 00 00 00 00 00 00 0 0 00 00 *
11 000000 ; 00 00 00 00 00 0000 0 0 000 000 *
12 000000 ; 000000 00000 0000 0000 00000 0000 0000 *
13 000000 ; *
14 000000 ; Case Name:Telecontrol Truck (SONIX SN8P1602B Inside) *
15 000000 ; Purpose :Receive RF information and control the truck *
16 000000 ; Version: 1.0 *
17 000000 ; Ooooo Author: Recal Chao *
18 000000 ; ooooO ( ) E-mail: sa1@sonix.cn *
19 000000 ; ( ) ) / Tel : (86)0755-26719666-235 *
20 000000 ; \ ( (_/ Fax : (86)0755-26719786 *
21 000000 ; \_) Date : 2004/05/10 *
22 000000 ; Company: SONIX TECHNOLOGY(SHENZHEN) CO.,LTD *
23 000000 ;*****************************************************************************
24 000000 ;Fosc=16MHz(Crystal)
25 000000 ;Fcpu=4MHz
26 000000 ;***************************************
27 000000 chip SN8P1602B
28 000000 //{{SONIX_CODE_OPTION
29 000000 .Code_Option Low_Power Disable
30 000000 .Code_Option Noise_Filter Enable
31 000000 .Code_Option OSG Enable
32 000000 .Code_Option High_Clk 12M_X'tal
33 000000 .Code_Option High_Clk/2 Disable
34 000000 .Code_Option Security Enable
35 000000 .Code_Option Int_16K_RC Always_ON
36 000000 .Code_Option Watch_Dog Enable
37 000000 //}}SONIX_CODE_OPTION
38 000000
39 000000 include ram.asm ; User's RAM and Pin Definition
40 000000 ;************************************************
41 000000 ; Main Program Data Define *
42 000000 ;************************************************
43 000000 .data
44 000000 ;===================Pin Difinition====================
45 E 000000D0 I_RF_receive equ P0.0
46 000000
47 E 000000D1 O_Music_Clk equ P1.0
48 E 000000C1 Om_Music_Clk equ P1M.0
49 E 000100D1 O_Music_Data0 equ P1.1
50 E 000100C1 Om_Music_Data0 equ P1M.1
51 E 000200D1 O_Music_Data1 equ P1.2
52 E 000200C1 Om_Music_Data1 equ P1M.2
53 000000
54 E 000000D2 O_Ctrl00 equ P2.0
55 E 000000C2 Om_Ctrl00 equ P2M.0
56 E 000100D2 O_Ctrl01 equ P2.1
57 E 000100C2 Om_Ctrl01 equ P2M.1
58 E 000200D2 O_Ctrl10 equ P2.2
59 E 000200C2 Om_Ctrl10 equ P2M.2
60 E 000300D2 O_Ctrl11 equ P2.3
61 E 000300C2 Om_Ctrl11 equ P2M.3
62 E 000400D2 O_Ctrl20 equ P2.4
63 E 000400C2 Om_Ctrl20 equ P2M.4
64 E 000500D2 O_Ctrl21 equ P2.5
65 E 000500C2 Om_Ctrl21 equ P2M.5
66 E 000600D2 O_left_Led equ P2.6
67 E 000600C2 Om_left_Led equ P2M.6
68 E 000700D2 O_right_Led equ P2.7
69 E 000700C2 Om_right_Led equ P2M.7
70 000000 ;=============== Usual work register =================
71 E 000000C0 IDcode equ #11000000b ;bit[5...0]=000000
72 0000 D motorflag ds 1
73 E 00000000 forward_f equ motorflag.0
74 E 00010000 backward_f equ motorflag.1
75 E 00020000 leftward_f equ motorflag.2
76 E 00030000 rightward_f equ motorflag.3
77 E 00040000 upward_f equ motorflag.4
78 E 00050000 downward_f equ motorflag.5
79 0001 D ledflag ds 1
80 E 00000001 leftled_f equ ledflag.0
81 E 00010001 rightled_f equ ledflag.1
82 0002 D forback_pwm ds 2
83 0004 D leftright_pwm ds 2
84 0006 D updown_pwm ds 2
85 0008 D motorstep ds 1
86 E 00000000 Noforbackval equ #00000000b ;
87 E 0000000F forwardval equ #00001111b ;1:1
88 E 0000003F fastforwardval equ #00111111b ;3:1
89 E 0000003F backwardval equ #00111111b ;3:1
90 E 0000000F slowbackwardval equ #00001111b ;1:1
91 E 00000000 Noleftrightval equ #00000000b ;
92 E 00000007 leftrightval equ #00000111b ;3:5
93 E 00000000 Noupdownval equ #00000000b ;
94 E 00000007 updownval equ #00000111b ;3:5
95 000009 ;RF receive information
96 0009 D RF_Time_step ds 1
97 000A D RFflag ds 1
98 E 00000008 RF_data_val equ #8
99 000B D RF_data_count ds 1
100 000C D RF_receivebuf ds 1
101 000D D RF_receiveRam ds 1
102 E 0000000A RF_pilot_detect_f equ RFflag.0
103 E 0001000A RF_receive_start_f equ RFflag.1
104 E 0002000A Time2ms_f equ RFflag.2
105 E 0003000A RF_receive_data_f equ RFflag.3
106 E 0004000A RF_step_ctr equ RFflag.4
107 E 0005000A RF_receive_finish equ RFflag.5
108 00000E
109 00000E ;================ Temp work register =================
110 000E D wk00 ds 1 ; Temp Register
111 00000F ;wk01 ds 1 ; X
112 00000F ;wk02 ds 1 ; X
113 00000F ;wk03 ds 1 ; X
114 00000F ;wk04 ds 1 ; X
115 00000F ;wk05 ds 1 ; X
116 00000F ;wk06 ds 1 ; X
117 00000F ;wk07 ds 1 ; X
118 00000F ;wk08 ds 1 ; X
119 00000F ;wk09 ds 1 ; X
120 00000F ;wk10 ds 1 ; X
121 00000F ;wk11 ds 1 ; X
122 00000F ;wk12 ds 1 ; Temp Register
123 00000F ;============================= Clear Ram =============================
124 E 00000001 @Rambank0 equ 1 ; 0: No bank0 ; 1: Have bank0
125 E 00000000 @Rambank1 equ 0 ; 0: No bank1 ; 1: Have bank1
126 E 00000000 @Rambank2 equ 0 ; 0: No bank2 ; 1: Have bank2
127 E 00000000 @Rambank3 equ 0 ; 0: No bank3 ; 1: Have bank3
128 E 00000000 @Rambank4 equ 0 ; 0: No bank4 ; 1: Have bank4
129 E 00000000 @Rambank15 equ 0 ; 0: No bank15 ; 1: Have bank15
130 E 00000030 @Rambank0_val equ #48 ; xx= 2fh,3fh,7fh...
131 00000F ;============================ Application =============================
132 00000F ; Power down
133 E 00000000 @Powerdown_set equ 0 ; 0: System not powerdown ; 1: System will power down
134 00000F ; Green mode
135 E 00000000 @GreenMode_set equ 0 ; 0: System not Greenmode ; 1: System will Greenmode
136 00000F ; Oscm setting
137 E 00000040 @Oscm_set equ #01000000b
138 00000F ; Pedge setting ; 0: Not use pedge register
139 E 00000002 @Pedge_set equ 2 ; 1: Wakeup by low level ; 2: Wakeup by falling edge
140 00000F ; 3: Wakeup by rising edge ; 4: Wakeup by change triggle
141 E 00000000 @Pedge_low_val equ #00000000b
142 E 00000088 @Pedge_fall_val equ #10001000b
143 E 00000090 @Pedge_rise_val equ #10010000b
144 E 00000098 @Pedge_triggle_val equ #10011000b
145 00000F ; A/D setting
146 E 00000000 @ADappl_set equ 0 ; 0: Not use A/D ; 1: Use A/D
147 00000F ; D/A setting
148 E 00000000 @DAappl_set equ 0 ; 0: Not use D/A ; 1: Use D/A
149 00000F ; LCD display
150 E 00000000 @Lcdappl_set equ 0 ; 0: Not use Lcd driver ; 1: Use Lcd driver
151 00000F ;============================== IO port ===============================
152 E 00000001 @ChipP0 equ 1 ; 1: P0 exist , 0: P0 not exist
153 E 00000001 @ChipP1 equ 1 ; 1: P1 exist , 0: P1 not exist
154 E 00000001 @ChipP2 equ 1 ; 1: P2 exist , 0: P2 not exist
155 E 00000000 @ChipP3 equ 0 ; 1: P3 exist , 0: P3 not exist
156 E 00000000 @ChipP4 equ 0 ; 1: P4 exist , 0: P4 not exist
157 E 00000000 @ChipP5 equ 0 ; 1: P5 exist , 0: P5 not exist
158 E 00000000 @ChipP6 equ 0 ; 1: P6 exist , 0: P6 not exist
159 E 00000000 @ChipP7 equ 0 ; 1: P7 exist , 0: P7 not exist
160 00000F
161 00000F ;Pur register Set/Port Value Set/IO direction Set
162 E 00000002 @Purmode equ 2 ; 0=No Pur register ; 1=Bit set ; 2=Port set
163 00000F ;----------------------------------------------
164 E 00000001 @Pur_set equ 00000001b ; Ex. 00110001b --> p0UR&p4UR&p5UR=1
165 00000F ;----------------------------------------------
166 00000F ;--------------
167 E 00000000 @p1set equ #00000000b ; In/Output value
168 E 00000000 @p1Wset equ #00000000b ; 0: No wakeup / 1: Wakeup
169 E 000000FF @p1Mset equ #11111111b ; 0: Input / 1: Output
170 00000F ;--------------
171 E 00000000 @p2set equ #00000000b ; In/Output value
172 E 000000FF @p2Mset equ #11111111b ; 0: Input / 1: Output
173 00000F ;--------------
174 00000F ;--------------
175 00000F ;--------------
176 00000F ;--------------
177 00000F ;--------------
178 00000F ;===================== Interrupt data Define ======================
179 000F D accbuf ds 1
180 0010 D pflagbuf ds 1
181 000011 ;ybuf ds 1
182 000011 ;zbuf ds 1
183 000011 ;rbuf ds 1
184 000011 ;xbuf ds 1
185 000011 ;hbuf ds 1
186 000011 ;lbuf ds 1
187 0011 D intwk00 ds 1 ;interrupt work register0
188 000012 ;intwk01 ds 1 ;interrupt work register1
189 000012 ;intwk02 ds 1 ;interrupt work register2
190 000012 ;intwk03 ds 1 ;interrupt work register3
191 000012 ;intwk04 ds 1 ;interrupt work register4
192 E 00000001 @ChipP00INT equ 1 ; 1: P00INT exist , 0: P00INT don't care
193 E 00000000 @ChipP01INT equ 0 ; 1: P00INT exist , 0: P00INT don't care
194 E 00000000 @ChipP02INT equ 0 ; 1: P00INT exist , 0: P00INT don't care
195 E 00000000 @ChipT0INT equ 0 ; 1: T0INT exist , 0: T0INT don't care
196 E 00000000 @ChipSIOINT equ 0 ; 1: SIOINT exist , 0: SIOINT don't care
197 E 00000001 @ChipTC0INT equ 1 ; 1: TC0INT exist , 0: TC0INT don't care
198 E 00000000 @ChipTC1INT equ 0 ; 1: TC1INT exist , 0: TC1INT don't care
199 E 00000000 @ChipADCINT equ 0 ; 1: ADINT exist , 0: ADINT don't care
200 000012 ;====================== Interrupt Interface data define =====================
201 000012
202 E 00000002 @Systimer_set equ 2 ;0: No system time base/1: T0 time base/2: Tc0 time base/3: Tc1 time base
203 000012
204 0012 D @intgnd ds 1 ;INT interface register
205 E 00000000 @SysT0 equ 0 ; 1: Use T0 / 0: Not use T0
206 E 00000001 @SysTc0 equ 1 ; 1: Use Tc0 / 0: Not use Tc0
207 E 00000000 @SysTc1 equ 0 ; 1: Use Tc1 / 0: Not use Tc1
208 000013
209 E 00000038 @SysTc0c equ #38h ; set Pre-scalar=fcpu/
210 E 00000060 @SysTc0m equ #60h ; set count steps
211 E 00000000 @SysTc0R_set equ 0 ; 1: Use Tc0R / 0: Not use TC0R
212 000013
213 E 00000000 IRQ=0
214 E 00000012 @Sys1msIRQ equ @intgnd.IRQ ;IRQ 5ms flag ;1ms
215 000013 IRQ=IRQ+1
216 E 00010012 @Sys2msIRQ equ @intgnd.IRQ ;IRQ 10ms flag ;2ms
217 000013 ;IRQ=IRQ+1
218 000013 ;@Sys50msIRQ equ @intgnd.IRQ ;IRQ 50ms flag
219 000013 ;IRQ=IRQ+1
220 000013 ;@Sys100msIRQ equ @intgnd.IRQ ;IRQ 100ms flag
221 000013 IRQ=IRQ+1
222 E 00020012 @Sys200msIRQ equ @intgnd.IRQ ;IRQ 200ms flag
223 000013 ;IRQ=IRQ+1
224 000013 ;@Sys300msIRQ equ @intgnd.IRQ ;IRQ 300ms flag
225 000013 ;IRQ=IRQ+1
226 000013 ;@Sys400msIRQ equ @intgnd.IRQ ;IRQ 400ms flag
227 000013 ;IRQ=IRQ+1
228 000013 ;@Sys500msIRQ equ @intgnd.IRQ ;IRQ 500ms flag
229 000013 ;IRQ=IRQ+1
230 000013 ;@Sys600msIRQQ equ @intgnd.IRQ ;IRQ 600ms flag
231 000013 ;IRQ=IRQ+1
232 000013 ;@Sys700msIRQ equ @intgnd.IRQ ;IRQ 700ms flag
233 000013 ;IRQ=IRQ+1
234 000013 ;@Sys800msIRQ equ @intgnd.IRQ ;IRQ 800ms flag
235 000013 ;IRQ=IRQ+1
236 000013 ;@Sys900msIRQ equ @intgnd.IRQ ;IRQ 900ms flag
237 000013 ;IRQ=IRQ+1
238 000013 ; @Sys1sIRQ equ @intgnd.IRQ ;IRQ 1000ms flag
239 000013 IRQ=IRQ+1
240 E 00030012 @Sys5sIRQ equ @intgnd.IRQ ;IRQ 5000ms flag ;1s
241 000013 ;IRQ=IRQ+1
242 000013 ;@Sys10sIRQ equ @intgnd.IRQ ;IRQ 10000ms flag
243 000013 ;IRQ=IRQ+1
244 000013 ;@Sys30sIRQ equ @intgnd.IRQ ;IRQ 30000ms flag
245 000013 ;IRQ=IRQ+1
246 000013 ;@Sys60sIRQ equ @intgnd.IRQ ;IRQ 60000ms flag
247 000013 ;IRQ=IRQ+1
248 000013 ;@Sys300sIRQ equ @intgnd.IRQ ;IRQ 300000ms flag
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