block1.sim.rpt

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

; |Block1|c24:inst9|count[5]            ; |Block1|c24:inst9|count[5]            ; regout           ;
; |Block1|c24:inst9|count[4]            ; |Block1|c24:inst9|count[4]            ; regout           ;
; |Block1|pwm4:inst5|LessThan0~66       ; |Block1|pwm4:inst5|LessThan0~66       ; combout          ;
; |Block1|c24:inst10|count[5]           ; |Block1|c24:inst10|count[5]           ; regout           ;
; |Block1|c24:inst10|count[4]           ; |Block1|c24:inst10|count[4]           ; regout           ;
; |Block1|c24:inst10|count[3]           ; |Block1|c24:inst10|count[3]           ; regout           ;
; |Block1|c24:inst10|count[2]           ; |Block1|c24:inst10|count[2]           ; regout           ;
; |Block1|pwm5:inst6|LessThan0~87       ; |Block1|pwm5:inst6|LessThan0~87       ; combout          ;
; |Block1|c24:inst7|count[1]            ; |Block1|c24:inst7|count[1]            ; regout           ;
; |Block1|c24:inst7|count[0]            ; |Block1|c24:inst7|count[0]            ; regout           ;
; |Block1|c24:inst8|count[1]            ; |Block1|c24:inst8|count[1]            ; regout           ;
; |Block1|c24:inst8|count[2]            ; |Block1|c24:inst8|count[2]            ; regout           ;
; |Block1|c24:inst8|count[0]            ; |Block1|c24:inst8|count[0]            ; regout           ;
; |Block1|c24:inst|count[1]             ; |Block1|c24:inst|count[1]             ; regout           ;
; |Block1|c24:inst|count[0]             ; |Block1|c24:inst|count[0]             ; regout           ;
; |Block1|c24:inst|count~264            ; |Block1|c24:inst|count~264            ; combout          ;
; |Block1|c24:inst|count~265            ; |Block1|c24:inst|count~265            ; combout          ;
; |Block1|c24:inst|count~266            ; |Block1|c24:inst|count~266            ; combout          ;
; |Block1|c24:inst|count[4]~267         ; |Block1|c24:inst|count[4]~267         ; combout          ;
; |Block1|c24:inst9|count[1]            ; |Block1|c24:inst9|count[1]            ; regout           ;
; |Block1|c24:inst9|count[3]            ; |Block1|c24:inst9|count[3]            ; regout           ;
; |Block1|c24:inst9|count[2]            ; |Block1|c24:inst9|count[2]            ; regout           ;
; |Block1|c24:inst9|count[0]            ; |Block1|c24:inst9|count[0]            ; regout           ;
; |Block1|c24:inst9|count~268           ; |Block1|c24:inst9|count~268           ; combout          ;
; |Block1|c24:inst9|count[4]~269        ; |Block1|c24:inst9|count[4]~269        ; combout          ;
; |Block1|c24:inst10|count[1]           ; |Block1|c24:inst10|count[1]           ; regout           ;
; |Block1|c24:inst10|count[0]           ; |Block1|c24:inst10|count[0]           ; regout           ;
; |Block1|c24:inst10|count~246          ; |Block1|c24:inst10|count~246          ; combout          ;
; |Block1|c24:inst10|count[4]~247       ; |Block1|c24:inst10|count[4]~247       ; combout          ;
; |Block1|c24:inst10|count~248          ; |Block1|c24:inst10|count~248          ; combout          ;
; |Block1|c24:inst|count~268            ; |Block1|c24:inst|count~268            ; combout          ;
; |Block1|c24:inst9|count~270           ; |Block1|c24:inst9|count~270           ; combout          ;
; |Block1|c24:inst9|count~271           ; |Block1|c24:inst9|count~271           ; combout          ;
; |Block1|c24:inst9|count~272           ; |Block1|c24:inst9|count~272           ; combout          ;
; |Block1|c24:inst10|count~249          ; |Block1|c24:inst10|count~249          ; combout          ;
; |Block1|c24:inst10|count~250          ; |Block1|c24:inst10|count~250          ; combout          ;
; |Block1|c24:inst7|count~270           ; |Block1|c24:inst7|count~270           ; combout          ;
; |Block1|c24:inst7|count~271           ; |Block1|c24:inst7|count~271           ; combout          ;
; |Block1|c24:inst7|count~272           ; |Block1|c24:inst7|count~272           ; combout          ;
; |Block1|c24:inst7|count[4]~273        ; |Block1|c24:inst7|count[4]~273        ; combout          ;
; |Block1|c24:inst7|count~274           ; |Block1|c24:inst7|count~274           ; combout          ;
; |Block1|c24:inst8|Equal1~37           ; |Block1|c24:inst8|Equal1~37           ; combout          ;
; |Block1|c24:inst8|count~263           ; |Block1|c24:inst8|count~263           ; combout          ;
; |Block1|c24:inst8|Equal0~25           ; |Block1|c24:inst8|Equal0~25           ; combout          ;
; |Block1|c24:inst8|count~264           ; |Block1|c24:inst8|count~264           ; combout          ;
; |Block1|c24:inst8|count~265           ; |Block1|c24:inst8|count~265           ; combout          ;
; |Block1|c24:inst8|count[4]~266        ; |Block1|c24:inst8|count[4]~266        ; combout          ;
; |Block1|c24:inst8|count~267           ; |Block1|c24:inst8|count~267           ; combout          ;
; |Block1|pwm2:inst3|LessThan0~67       ; |Block1|pwm2:inst3|LessThan0~67       ; combout          ;
; |Block1|c24:inst7|count[0]~275        ; |Block1|c24:inst7|count[0]~275        ; combout          ;
; |Block1|c24:inst8|count[0]~268        ; |Block1|c24:inst8|count[0]~268        ; combout          ;
; |Block1|c24:inst|count[0]~269         ; |Block1|c24:inst|count[0]~269         ; combout          ;
; |Block1|c24:inst9|count[0]~273        ; |Block1|c24:inst9|count[0]~273        ; combout          ;
; |Block1|c24:inst10|count[0]~251       ; |Block1|c24:inst10|count[0]~251       ; combout          ;
; |Block1|pwm1                          ; |Block1|pwm1                          ; padio            ;
; |Block1|pwm2                          ; |Block1|pwm2                          ; padio            ;
; |Block1|pwm3                          ; |Block1|pwm3                          ; padio            ;
; |Block1|pwm4                          ; |Block1|pwm4                          ; padio            ;
; |Block1|pwm5                          ; |Block1|pwm5                          ; padio            ;
; |Block1|clk1                          ; |Block1|clk1~corein                   ; combout          ;
; |Block1|clk2                          ; |Block1|clk2~corein                   ; combout          ;
; |Block1|clk3                          ; |Block1|clk3~corein                   ; combout          ;
; |Block1|clk4                          ; |Block1|clk4~corein                   ; combout          ;
; |Block1|clk5                          ; |Block1|clk5~corein                   ; combout          ;
; |Block1|clk1~clkctrl                  ; |Block1|clk1~clkctrl                  ; outclk           ;
; |Block1|clk5~clkctrl                  ; |Block1|clk5~clkctrl                  ; outclk           ;
; |Block1|clk2~clkctrl                  ; |Block1|clk2~clkctrl                  ; outclk           ;
; |Block1|clk4~clkctrl                  ; |Block1|clk4~clkctrl                  ; outclk           ;
; |Block1|clk3~clkctrl                  ; |Block1|clk3~clkctrl                  ; outclk           ;
; |Block1|c24:inst|count~265DUPLICATE   ; |Block1|c24:inst|count~265DUPLICATE   ; combout          ;
; |Block1|c24:inst|count[2]~DUPLICATE   ; |Block1|c24:inst|count[2]~DUPLICATE   ; regout           ;
; |Block1|c24:inst9|count~272DUPLICATE  ; |Block1|c24:inst9|count~272DUPLICATE  ; combout          ;
; |Block1|c24:inst9|count[2]~DUPLICATE  ; |Block1|c24:inst9|count[2]~DUPLICATE  ; regout           ;
; |Block1|c24:inst10|count~250DUPLICATE ; |Block1|c24:inst10|count~250DUPLICATE ; combout          ;
; |Block1|c24:inst10|count[2]~DUPLICATE ; |Block1|c24:inst10|count[2]~DUPLICATE ; regout           ;
; |Block1|c24:inst7|count~271DUPLICATE  ; |Block1|c24:inst7|count~271DUPLICATE  ; combout          ;
; |Block1|c24:inst7|count[2]~DUPLICATE  ; |Block1|c24:inst7|count[2]~DUPLICATE  ; regout           ;
; |Block1|c24:inst8|Equal1~37DUPLICATE  ; |Block1|c24:inst8|Equal1~37DUPLICATE  ; combout          ;
+---------------------------------------+---------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jul 29 12:39:49 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Block1 -c Block1
Info: Using vector source file "F:/FPGA/1/Block1.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is     100.00 %
Info: Number of transitions in simulation is 2796
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Tue Jul 29 12:39:52 2008
    Info: Elapsed time: 00:00:03