block1.fit.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 12:37:25 2008 " "Info: Processing started: Tue Jul 29 12:37:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Block1 -c Block1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Block1 -c Block1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "Block1 EP2S15F484C3 " "Info: Automatically selected device EP2S15F484C3 for design Block1" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "77 Top " "Info: Previous placement does not exist for 77 of 77 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S30F484C3 " "Info: Device EP2S30F484C3 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S60F484C3 " "Info: Device EP2S60F484C3 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S60F484C3ES " "Info: Device EP2S60F484C3ES is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "10 10 " "Warning: No exact pin location assignment(s) for 10 pins of 10 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pwm1 " "Info: Pin pwm1 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { pwm1 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 952 1128 248 "pwm1" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm1 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pwm2 " "Info: Pin pwm2 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { pwm2 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 352 936 1112 368 "pwm2" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm2 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pwm3 " "Info: Pin pwm3 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { pwm3 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 928 1104 480 "pwm3" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm3 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pwm4 " "Info: Pin pwm4 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { pwm4 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 928 1104 592 "pwm4" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm4 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pwm5 " "Info: Pin pwm5 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { pwm5 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 944 1120 704 "pwm5" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm5 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk1 " "Info: Pin clk1 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk1 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk2 " "Info: Pin clk2 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk2 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 352 256 424 368 "clk2" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk3 " "Info: Pin clk3 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk3 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk4 " "Info: Pin clk4 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk4 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk5 " "Info: Pin clk5 not assigned to an exact location on the device" {  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk5 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk5 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk1 (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk1 (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk1 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk2 (placed in PIN M21 (CLK1p, Input)) " "Info: Automatically promoted node clk2 (placed in PIN M21 (CLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk2 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 352 256 424 368 "clk2" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk3 (placed in PIN M2 (CLK11p, Input)) " "Info: Automatically promoted node clk3 (placed in PIN M2 (CLK11p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartusii/quartus/bin/pin_planner.ppl" { clk3 } } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}