prev_cmp_block1.map.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 12:36:48 2008 " "Info: Processing started: Tue Jul 29 12:36:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Block1 -c Block1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Block1 -c Block1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm2-one " "Info: Found design unit 1: pwm2-one" {  } { { "pwm2.vhd" "" { Text "F:/FPGA/1/pwm2.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm2 " "Info: Found entity 1: pwm2" {  } { { "pwm2.vhd" "" { Text "F:/FPGA/1/pwm2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm3-one " "Info: Found design unit 1: pwm3-one" {  } { { "pwm3.vhd" "" { Text "F:/FPGA/1/pwm3.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm3 " "Info: Found entity 1: pwm3" {  } { { "pwm3.vhd" "" { Text "F:/FPGA/1/pwm3.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm4-one " "Info: Found design unit 1: pwm4-one" {  } { { "pwm4.vhd" "" { Text "F:/FPGA/1/pwm4.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm4 " "Info: Found entity 1: pwm4" {  } { { "pwm4.vhd" "" { Text "F:/FPGA/1/pwm4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm5-one " "Info: Found design unit 1: pwm5-one" {  } { { "pwm5.vhd" "" { Text "F:/FPGA/1/pwm5.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm5 " "Info: Found entity 1: pwm5" {  } { { "pwm5.vhd" "" { Text "F:/FPGA/1/pwm5.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "Block1.bdf 1 1 " "Warning: Using design file Block1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EGDFX_DUPLICATE_DEFINITION" "clk " "Error: Illegal name \"clk\" -- pin name already exists" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 352 256 424 368 "clk" "" } { 232 256 424 248 "clk" "" } } } }  } 0 0 "Illegal name \"%1!s!\" -- pin name already exists" 0 0 "" 0}
{ "Error" "EGDFX_DUPLICATE_DEFINITION" "clk " "Error: Illegal name \"clk\" -- pin name already exists" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk" "" } { 232 256 424 248 "clk" "" } } } }  } 0 0 "Illegal name \"%1!s!\" -- pin name already exists" 0 0 "" 0}
{ "Error" "EGDFX_DUPLICATE_DEFINITION" "clk " "Error: Illegal name \"clk\" -- pin name already exists" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk" "" } { 232 256 424 248 "clk" "" } } } }  } 0 0 "Illegal name \"%1!s!\" -- pin name already exists" 0 0 "" 0}
{ "Error" "EGDFX_DUPLICATE_DEFINITION" "clk " "Error: Illegal name \"clk\" -- pin name already exists" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk" "" } { 232 256 424 248 "clk" "" } } } }  } 0 0 "Illegal name \"%1!s!\" -- pin name already exists" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 5 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Tue Jul 29 12:36:51 2008 " "Error: Processing ended: Tue Jul 29 12:36:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}