block1.tan.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk5 register register c24:inst10\|count\[4\] c24:inst10\|count\[5\] 500.0 MHz Internal " "Info: Clock \"clk5\" Internal fmax is restricted to 500.0 MHz between source register \"c24:inst10\|count\[4\]\" and destination register \"c24:inst10\|count\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.827 ns + Longest register register " "Info: + Longest register to register delay is 0.827 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c24:inst10\|count\[4\] 1 REG LCFF_X39_Y1_N17 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y1_N17; Fanout = 5; REG Node = 'c24:inst10\|count\[4\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst10|count[4] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.294 ns) + CELL(0.378 ns) 0.672 ns c24:inst10\|count~246 2 COMB LCCOMB_X39_Y1_N2 1 " "Info: 2: + IC(0.294 ns) + CELL(0.378 ns) = 0.672 ns; Loc. = LCCOMB_X39_Y1_N2; Fanout = 1; COMB Node = 'c24:inst10\|count~246'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.672 ns" { c24:inst10|count[4] c24:inst10|count~246 } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.827 ns c24:inst10\|count\[5\] 3 REG LCFF_X39_Y1_N3 4 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.827 ns; Loc. = LCFF_X39_Y1_N3; Fanout = 4; REG Node = 'c24:inst10\|count\[5\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { c24:inst10|count~246 c24:inst10|count[5] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.533 ns ( 64.45 % ) " "Info: Total cell delay = 0.533 ns ( 64.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.294 ns ( 35.55 % ) " "Info: Total interconnect delay = 0.294 ns ( 35.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.827 ns" { c24:inst10|count[4] c24:inst10|count~246 c24:inst10|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.827 ns" { c24:inst10|count[4] {} c24:inst10|count~246 {} c24:inst10|count[5] {} } { 0.000ns 0.294ns 0.000ns } { 0.000ns 0.378ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk5 destination 2.524 ns + Shortest register " "Info: + Shortest clock path from clock \"clk5\" to destination register is 2.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk5 1 CLK PIN_N22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N22; Fanout = 1; CLK Node = 'clk5'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk5 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.000 ns) 1.218 ns clk5~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.218 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk5~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.354 ns" { clk5 clk5~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.618 ns) 2.524 ns c24:inst10\|count\[5\] 3 REG LCFF_X39_Y1_N3 4 " "Info: 3: + IC(0.688 ns) + CELL(0.618 ns) = 2.524 ns; Loc. = LCFF_X39_Y1_N3; Fanout = 4; REG Node = 'c24:inst10\|count\[5\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.306 ns" { clk5~clkctrl c24:inst10|count[5] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.482 ns ( 58.72 % ) " "Info: Total cell delay = 1.482 ns ( 58.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.042 ns ( 41.28 % ) " "Info: Total interconnect delay = 1.042 ns ( 41.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.524 ns" { clk5 clk5~clkctrl c24:inst10|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.524 ns" { clk5 {} clk5~combout {} clk5~clkctrl {} c24:inst10|count[5] {} } { 0.000ns 0.000ns 0.354ns 0.688ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk5 source 2.524 ns - Longest register " "Info: - Longest clock path from clock \"clk5\" to source register is 2.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk5 1 CLK PIN_N22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N22; Fanout = 1; CLK Node = 'clk5'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk5 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.000 ns) 1.218 ns clk5~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.218 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk5~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.354 ns" { clk5 clk5~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.618 ns) 2.524 ns c24:inst10\|count\[4\] 3 REG LCFF_X39_Y1_N17 5 " "Info: 3: + IC(0.688 ns) + CELL(0.618 ns) = 2.524 ns; Loc. = LCFF_X39_Y1_N17; Fanout = 5; REG Node = 'c24:inst10\|count\[4\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.306 ns" { clk5~clkctrl c24:inst10|count[4] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.482 ns ( 58.72 % ) " "Info: Total cell delay = 1.482 ns ( 58.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.042 ns ( 41.28 % ) " "Info: Total interconnect delay = 1.042 ns ( 41.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.524 ns" { clk5 clk5~clkctrl c24:inst10|count[4] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.524 ns" { clk5 {} clk5~combout {} clk5~clkctrl {} c24:inst10|count[4] {} } { 0.000ns 0.000ns 0.354ns 0.688ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.524 ns" { clk5 clk5~clkctrl c24:inst10|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.524 ns" { clk5 {} clk5~combout {} clk5~clkctrl {} c24:inst10|count[5] {} } { 0.000ns 0.000ns 0.354ns 0.688ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.524 ns" { clk5 clk5~clkctrl c24:inst10|count[4] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.524 ns" { clk5 {} clk5~combout {} clk5~clkctrl {} c24:inst10|count[4] {} } { 0.000ns 0.000ns 0.354ns 0.688ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.827 ns" { c24:inst10|count[4] c24:inst10|count~246 c24:inst10|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.827 ns" { c24:inst10|count[4] {} c24:inst10|count~246 {} c24:inst10|count[5] {} } { 0.000ns 0.294ns 0.000ns } { 0.000ns 0.378ns 0.155ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.524 ns" { clk5 clk5~clkctrl c24:inst10|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quar