block1.tan.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk3 register register c24:inst\|count\[4\] c24:inst\|count\[2\] 500.0 MHz Internal " "Info: Clock \"clk3\" Internal fmax is restricted to 500.0 MHz between source register \"c24:inst\|count\[4\]\" and destination register \"c24:inst\|count\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.875 ns + Longest register register " "Info: + Longest register to register delay is 0.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c24:inst\|count\[4\] 1 REG LCFF_X30_Y26_N21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y26_N21; Fanout = 5; REG Node = 'c24:inst\|count\[4\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst|count[4] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.357 ns) 0.720 ns c24:inst\|count~265 2 COMB LCCOMB_X30_Y26_N0 1 " "Info: 2: + IC(0.363 ns) + CELL(0.357 ns) = 0.720 ns; Loc. = LCCOMB_X30_Y26_N0; Fanout = 1; COMB Node = 'c24:inst\|count~265'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.720 ns" { c24:inst|count[4] c24:inst|count~265 } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.875 ns c24:inst\|count\[2\] 3 REG LCFF_X30_Y26_N1 5 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.875 ns; Loc. = LCFF_X30_Y26_N1; Fanout = 5; REG Node = 'c24:inst\|count\[2\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { c24:inst|count~265 c24:inst|count[2] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.512 ns ( 58.51 % ) " "Info: Total cell delay = 0.512 ns ( 58.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.363 ns ( 41.49 % ) " "Info: Total interconnect delay = 0.363 ns ( 41.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.875 ns" { c24:inst|count[4] c24:inst|count~265 c24:inst|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.875 ns" { c24:inst|count[4] {} c24:inst|count~265 {} c24:inst|count[2] {} } { 0.000ns 0.363ns 0.000ns } { 0.000ns 0.357ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk3 destination 2.512 ns + Shortest register " "Info: + Shortest clock path from clock \"clk3\" to destination register is 2.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk3 1 CLK PIN_M2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 1; CLK Node = 'clk3'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns clk3~clkctrl 2 COMB CLKCTRL_G9 7 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G9; Fanout = 7; COMB Node = 'clk3~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk3 clk3~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.618 ns) 2.512 ns c24:inst\|count\[2\] 3 REG LCFF_X30_Y26_N1 5 " "Info: 3: + IC(0.687 ns) + CELL(0.618 ns) = 2.512 ns; Loc. = LCFF_X30_Y26_N1; Fanout = 5; REG Node = 'c24:inst\|count\[2\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.305 ns" { clk3~clkctrl c24:inst|count[2] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.482 ns ( 59.00 % ) " "Info: Total cell delay = 1.482 ns ( 59.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns ( 41.00 % ) " "Info: Total interconnect delay = 1.030 ns ( 41.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { clk3 clk3~clkctrl c24:inst|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { clk3 {} clk3~combout {} clk3~clkctrl {} c24:inst|count[2] {} } { 0.000ns 0.000ns 0.343ns 0.687ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk3 source 2.512 ns - Longest register " "Info: - Longest clock path from clock \"clk3\" to source register is 2.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk3 1 CLK PIN_M2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 1; CLK Node = 'clk3'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns clk3~clkctrl 2 COMB CLKCTRL_G9 7 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G9; Fanout = 7; COMB Node = 'clk3~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk3 clk3~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.618 ns) 2.512 ns c24:inst\|count\[4\] 3 REG LCFF_X30_Y26_N21 5 " "Info: 3: + IC(0.687 ns) + CELL(0.618 ns) = 2.512 ns; Loc. = LCFF_X30_Y26_N21; Fanout = 5; REG Node = 'c24:inst\|count\[4\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.305 ns" { clk3~clkctrl c24:inst|count[4] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.482 ns ( 59.00 % ) " "Info: Total cell delay = 1.482 ns ( 59.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns ( 41.00 % ) " "Info: Total interconnect delay = 1.030 ns ( 41.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { clk3 clk3~clkctrl c24:inst|count[4] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { clk3 {} clk3~combout {} clk3~clkctrl {} c24:inst|count[4] {} } { 0.000ns 0.000ns 0.343ns 0.687ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { clk3 clk3~clkctrl c24:inst|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { clk3 {} clk3~combout {} clk3~clkctrl {} c24:inst|count[2] {} } { 0.000ns 0.000ns 0.343ns 0.687ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { clk3 clk3~clkctrl c24:inst|count[4] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { clk3 {} clk3~combout {} clk3~clkctrl {} c24:inst|count[4] {} } { 0.000ns 0.000ns 0.343ns 0.687ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.875 ns" { c24:inst|count[4] c24:inst|count~265 c24:inst|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.875 ns" { c24:inst|count[4] {} c24:inst|count~265 {} c24:inst|count[2] {} } { 0.000ns 0.363ns 0.000ns } { 0.000ns 0.357ns 0.155ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { clk3 clk3~clkctrl c24:inst|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { clk3 {} clk3~combout {} clk3~clkctrl {} c24:inst|count[2] {} } { 0.000ns 0.000ns 0.343ns 0.687ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { clk3 clk3~clkctrl c24:inst|count[4] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { clk3 {} clk3~combout {} clk3~clkctrl {} c24:inst|count[4] {} } { 0.000ns 0.000ns 0.343ns 0.687ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c24:inst|count[2] {} } {  } {  } "" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk4 register register c24:inst9\|count\[1\] c24:inst9\|count\[2\] 500.0 MHz Internal " "Info: Clock \"clk4\" Internal fmax is restricted to 500.0 MHz between source register \"c24:inst9\|count\[1\]\" and destination register \"c24:inst9\|count\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.931 ns + Longest register register " "Info: + Longest register to register delay is 0.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c24:inst9\|count\[1\] 1 REG LCFF_X14_Y26_N13 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y26_N13; Fanout = 6; REG Node = 'c24:inst9\|count\[1\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst9|count[1] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.357 ns) 0.776 ns c24:inst9\|count~272 2 COMB LCCOMB_X14_Y26_N16 1 " "Info: 2: + IC(0.419 ns) + CELL(0.357 ns) = 0.776 ns; Loc. = LCCOMB_X14_Y26_N16; Fanout = 1; COMB Node = 'c24:inst9\|count~272'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { c24:inst9|count[1] c24:inst9|count~272 } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.931 ns c24:inst9\|count\[2\] 3 REG LCFF_X14_Y26_N17 4 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.931 ns; Loc. = LCFF_X14_Y26_N17; Fanout = 4; REG Node = 'c24:inst9\|count\[2\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { c24:inst9|count~272 c24:inst9|count[2] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.512 ns ( 54.99 % ) " "Info: Total cell delay = 0.512 ns ( 54.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.419 ns ( 45.01 % ) " "Info: Total interconnect delay = 0.419 ns ( 45.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.931 ns" { c24:inst9|count[1] c24:inst9|count~272 c24:inst9|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.931 ns" { c24:inst9|count[1] {} c24:inst9|count~272 {} c24:inst9|count[2] {} } { 0.000ns 0.419ns 0.000ns } { 0.000ns 0.357ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 destination 2.485 ns + Shortest register " "Info: + Shortest clock path from clock \"clk4\" to destination register is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk4 1 CLK PIN_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N3; Fanout = 1; CLK Node = 'clk4'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk4~clkctrl 2 COMB CLKCTRL_G11 7 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G11; Fanout = 7; COMB Node = 'clk4~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk4 clk4~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.485 ns c24:inst9\|count\[2\] 3 REG LCFF_X14_Y26_N17 4 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X14_Y26_N17; Fanout = 4; REG Node = 'c24:inst9\|count\[2\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { clk4~clkctrl c24:inst9|count[2] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.24 % ) " "Info: Total cell delay = 1.472 ns ( 59.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.76 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk4 clk4~clkctrl c24:inst9|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} c24:inst9|count[2] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 source 2.485 ns - Longest register " "Info: - Longest clock path from clock \"clk4\" to source register is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk4 1 CLK PIN_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N3; Fanout = 1; CLK Node = 'clk4'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk4~clkctrl 2 COMB CLKCTRL_G11 7 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G11; Fanout = 7; COMB Node = 'clk4~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk4 clk4~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.485 ns c24:inst9\|count\[1\] 3 REG LCFF_X14_Y26_N13 6 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X14_Y26_N13; Fanout = 6; REG Node = 'c24:inst9\|count\[1\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { clk4~clkctrl c24:inst9|count[1] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.24 % ) " "Info: Total cell delay = 1.472 ns ( 59.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.76 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk4 clk4~clkctrl c24:inst9|count[1] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} c24:inst9|count[1] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk4 clk4~clkctrl c24:inst9|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} c24:inst9|count[2] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk4 clk4~clkctrl c24:inst9|count[1] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} c24:inst9|count[1] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.931 ns" { c24:inst9|count[1] c24:inst9|count~272 c24:inst9|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.931 ns" { c24:inst9|count[1] {} c24:inst9|count~272 {} c24:inst9|count[2] {} } { 0.000ns 0.419ns 0.000ns } { 0.000ns 0.357ns 0.155ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk4 clk4~clkctrl c24:inst9|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} c24:inst9|count[2] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk4 clk4~clkctrl c24:inst9|count[1] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} c24:inst9|count[1] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst9|count[2] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c24:inst9|count[2] {} } {  } {  } "" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}