block1.tan.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Block1 -c Block1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Block1 -c Block1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 352 256 424 368 "clk2" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk3 " "Info: Assuming node \"clk3\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk4 " "Info: Assuming node \"clk4\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk4" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk5 " "Info: Assuming node \"clk5\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk5" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}