prev_cmp_block1.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/FPGA/1/Block1.fit.smsg " "Info: Generated suppressed messages file F:/FPGA/1/Block1.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "190 " "Info: Allocated 190 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 29 12:37:36 2008 " "Info: Processing ended: Tue Jul 29 12:37:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 12:37:38 2008 " "Info: Processing started: Tue Jul 29 12:37:38 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Block1 -c Block1 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Block1 -c Block1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "168 " "Info: Allocated 168 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 29 12:37:48 2008 " "Info: Processing ended: Tue Jul 29 12:37:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 12:37:50 2008 " "Info: Processing started: Tue Jul 29 12:37:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Block1 -c Block1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Block1 -c Block1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 352 256 424 368 "clk2" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk3 " "Info: Assuming node \"clk3\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 464 256 424 480 "clk3" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk4 " "Info: Assuming node \"clk4\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 576 256 424 592 "clk4" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk4" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk5 " "Info: Assuming node \"clk5\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 688 264 432 704 "clk5" "" } } } } { "f:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk5" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk1 register register c24:inst7\|count\[3\] c24:inst7\|count\[2\]~DUPLICATE 500.0 MHz Internal " "Info: Clock \"clk1\" Internal fmax is restricted to 500.0 MHz between source register \"c24:inst7\|count\[3\]\" and destination register \"c24:inst7\|count\[2\]~DUPLICATE\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.908 ns + Longest register register " "Info: + Longest register to register delay is 0.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c24:inst7\|count\[3\] 1 REG LCFF_X39_Y4_N15 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y4_N15; Fanout = 7; REG Node = 'c24:inst7\|count\[3\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst7|count[3] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.378 ns) 0.753 ns c24:inst7\|count~271DUPLICATE 2 COMB LCCOMB_X39_Y4_N2 1 " "Info: 2: + IC(0.375 ns) + CELL(0.378 ns) = 0.753 ns; Loc. = LCCOMB_X39_Y4_N2; Fanout = 1; COMB Node = 'c24:inst7\|count~271DUPLICATE'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.753 ns" { c24:inst7|count[3] c24:inst7|count~271DUPLICATE } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.908 ns c24:inst7\|count\[2\]~DUPLICATE 3 REG LCFF_X39_Y4_N3 4 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.908 ns; Loc. = LCFF_X39_Y4_N3; Fanout = 4; REG Node = 'c24:inst7\|count\[2\]~DUPLICATE'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { c24:inst7|count~271DUPLICATE c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.533 ns ( 58.70 % ) " "Info: Total cell delay = 0.533 ns ( 58.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.375 ns ( 41.30 % ) " "Info: Total interconnect delay = 0.375 ns ( 41.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { c24:inst7|count[3] c24:inst7|count~271DUPLICATE c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.908 ns" { c24:inst7|count[3] {} c24:inst7|count~271DUPLICATE {} c24:inst7|count[2]~DUPLICATE {} } { 0.000ns 0.375ns 0.000ns } { 0.000ns 0.378ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.495 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 7 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk1~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.618 ns) 2.495 ns c24:inst7\|count\[2\]~DUPLICATE 3 REG LCFF_X39_Y4_N3 4 " "Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X39_Y4_N3; Fanout = 4; REG Node = 'c24:inst7\|count\[2\]~DUPLICATE'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.298 ns" { clk1~clkctrl c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.00 % ) " "Info: Total cell delay = 1.472 ns ( 59.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.023 ns ( 41.00 % ) " "Info: Total interconnect delay = 1.023 ns ( 41.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk1 clk1~clkctrl c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} c24:inst7|count[2]~DUPLICATE {} } { 0.000ns 0.000ns 0.343ns 0.680ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.495 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 7 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk1~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 232 256 424 248 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.618 ns) 2.495 ns c24:inst7\|count\[3\] 3 REG LCFF_X39_Y4_N15 7 " "Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X39_Y4_N15; Fanout = 7; REG Node = 'c24:inst7\|count\[3\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.298 ns" { clk1~clkctrl c24:inst7|count[3] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.00 % ) " "Info: Total cell delay = 1.472 ns ( 59.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.023 ns ( 41.00 % ) " "Info: Total interconnect delay = 1.023 ns ( 41.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk1 clk1~clkctrl c24:inst7|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} c24:inst7|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.680ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk1 clk1~clkctrl c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} c24:inst7|count[2]~DUPLICATE {} } { 0.000ns 0.000ns 0.343ns 0.680ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk1 clk1~clkctrl c24:inst7|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} c24:inst7|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.680ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { c24:inst7|count[3] c24:inst7|count~271DUPLICATE c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.908 ns" { c24:inst7|count[3] {} c24:inst7|count~271DUPLICATE {} c24:inst7|count[2]~DUPLICATE {} } { 0.000ns 0.375ns 0.000ns } { 0.000ns 0.378ns 0.155ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk1 clk1~clkctrl c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} c24:inst7|count[2]~DUPLICATE {} } { 0.000ns 0.000ns 0.343ns 0.680ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk1 clk1~clkctrl c24:inst7|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} c24:inst7|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.680ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst7|count[2]~DUPLICATE } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c24:inst7|count[2]~DUPLICATE {} } {  } {  } "" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk2 register register c24:inst8\|count\[3\] c24:inst8\|count\[5\] 500.0 MHz Internal " "Info: Clock \"clk2\" Internal fmax is restricted to 500.0 MHz between source register \"c24:inst8\|count\[3\]\" and destination register \"c24:inst8\|count\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.398 ns + Longest register register " "Info: + Long