prev_cmp_block1.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 12:37:20 2008 " "Info: Processing started: Tue Jul 29 12:37:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Block1 -c Block1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Block1 -c Block1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm2-one " "Info: Found design unit 1: pwm2-one" {  } { { "pwm2.vhd" "" { Text "F:/FPGA/1/pwm2.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm2 " "Info: Found entity 1: pwm2" {  } { { "pwm2.vhd" "" { Text "F:/FPGA/1/pwm2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm3-one " "Info: Found design unit 1: pwm3-one" {  } { { "pwm3.vhd" "" { Text "F:/FPGA/1/pwm3.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm3 " "Info: Found entity 1: pwm3" {  } { { "pwm3.vhd" "" { Text "F:/FPGA/1/pwm3.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm4-one " "Info: Found design unit 1: pwm4-one" {  } { { "pwm4.vhd" "" { Text "F:/FPGA/1/pwm4.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm4 " "Info: Found entity 1: pwm4" {  } { { "pwm4.vhd" "" { Text "F:/FPGA/1/pwm4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm5-one " "Info: Found design unit 1: pwm5-one" {  } { { "pwm5.vhd" "" { Text "F:/FPGA/1/pwm5.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm5 " "Info: Found entity 1: pwm5" {  } { { "pwm5.vhd" "" { Text "F:/FPGA/1/pwm5.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "Block1.bdf 1 1 " "Warning: Using design file Block1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "pwm.vhd 2 1 " "Warning: Using design file pwm.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm-one " "Info: Found design unit 1: pwm-one" {  } { { "pwm.vhd" "" { Text "F:/FPGA/1/pwm.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Info: Found entity 1: pwm" {  } { { "pwm.vhd" "" { Text "F:/FPGA/1/pwm.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:inst1 " "Info: Elaborating entity \"pwm\" for hierarchy \"pwm:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 728 848 304 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "c24.vhd 2 1 " "Warning: Using design file c24.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 c24-Behavioral " "Info: Found design unit 1: c24-Behavioral" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 c24 " "Info: Found entity 1: c24" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "c24 c24:inst7 " "Info: Elaborating entity \"c24\" for hierarchy \"c24:inst7\"" {  } { { "Block1.bdf" "inst7" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 424 536 304 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count c24.vhd(24) " "Warning (10492): VHDL Process Statement warning at c24.vhd(24): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm2 pwm2:inst3 " "Info: Elaborating entity \"pwm2\" for hierarchy \"pwm2:inst3\"" {  } { { "Block1.bdf" "inst3" { Schematic "F:/FPGA/1/Block1.bdf" { { 328 728 856 424 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm3 pwm3:inst4 " "Info: Elaborating entity \"pwm3\" for hierarchy \"pwm3:inst4\"" {  } { { "Block1.bdf" "inst4" { Schematic "F:/FPGA/1/Block1.bdf" { { 440 736 864 536 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm4 pwm4:inst5 " "Info: Elaborating entity \"pwm4\" for hierarchy \"pwm4:inst5\"" {  } { { "Block1.bdf" "inst5" { Schematic "F:/FPGA/1/Block1.bdf" { { 552 736 864 648 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm5 pwm5:inst6 " "Info: Elaborating entity \"pwm5\" for hierarchy \"pwm5:inst6\"" {  } { { "Block1.bdf" "inst6" { Schematic "F:/FPGA/1/Block1.bdf" { { 664 736 864 760 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}