prev_cmp_block1.tan.qmsg

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "pin_name register register c24:inst\|count\[3\] c24:inst\|count\[5\] 500.0 MHz Internal " "Info: Clock \"pin_name\" Internal fmax is restricted to 500.0 MHz between source register \"c24:inst\|count\[3\]\" and destination register \"c24:inst\|count\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.432 ns + Longest register register " "Info: + Longest register to register delay is 1.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c24:inst\|count\[3\] 1 REG LCFF_X26_Y26_N27 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y26_N27; Fanout = 4; REG Node = 'c24:inst\|count\[3\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst|count[3] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.378 ns) 0.663 ns c24:inst\|Equal1~41 2 COMB LCCOMB_X26_Y26_N28 4 " "Info: 2: + IC(0.285 ns) + CELL(0.378 ns) = 0.663 ns; Loc. = LCCOMB_X26_Y26_N28; Fanout = 4; COMB Node = 'c24:inst\|Equal1~41'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.663 ns" { c24:inst|count[3] c24:inst|Equal1~41 } "NODE_NAME" } } { "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.346 ns) 1.277 ns c24:inst\|count~267 3 COMB LCCOMB_X26_Y26_N24 1 " "Info: 3: + IC(0.268 ns) + CELL(0.346 ns) = 1.277 ns; Loc. = LCCOMB_X26_Y26_N24; Fanout = 1; COMB Node = 'c24:inst\|count~267'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.614 ns" { c24:inst|Equal1~41 c24:inst|count~267 } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.432 ns c24:inst\|count\[5\] 4 REG LCFF_X26_Y26_N25 3 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.432 ns; Loc. = LCFF_X26_Y26_N25; Fanout = 3; REG Node = 'c24:inst\|count\[5\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { c24:inst|count~267 c24:inst|count[5] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.879 ns ( 61.38 % ) " "Info: Total cell delay = 0.879 ns ( 61.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 38.62 % ) " "Info: Total interconnect delay = 0.553 ns ( 38.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.432 ns" { c24:inst|count[3] c24:inst|Equal1~41 c24:inst|count~267 c24:inst|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.432 ns" { c24:inst|count[3] {} c24:inst|Equal1~41 {} c24:inst|count~267 {} c24:inst|count[5] {} } { 0.000ns 0.285ns 0.268ns 0.000ns } { 0.000ns 0.378ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_name destination 2.498 ns + Shortest register " "Info: + Shortest clock path from clock \"pin_name\" to destination register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns pin_name 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'pin_name'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_name } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 240 408 224 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns pin_name~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'pin_name~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { pin_name pin_name~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 240 408 224 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns c24:inst\|count\[5\] 3 REG LCFF_X26_Y26_N25 3 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X26_Y26_N25; Fanout = 3; REG Node = 'c24:inst\|count\[5\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { pin_name~clkctrl c24:inst|count[5] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[5] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_name source 2.498 ns - Longest register " "Info: - Longest clock path from clock \"pin_name\" to source register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns pin_name 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'pin_name'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_name } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 240 408 224 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns pin_name~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'pin_name~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { pin_name pin_name~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 240 408 224 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns c24:inst\|count\[3\] 3 REG LCFF_X26_Y26_N27 4 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X26_Y26_N27; Fanout = 4; REG Node = 'c24:inst\|count\[3\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[5] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.432 ns" { c24:inst|count[3] c24:inst|Equal1~41 c24:inst|count~267 c24:inst|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.432 ns" { c24:inst|count[3] {} c24:inst|Equal1~41 {} c24:inst|count~267 {} c24:inst|count[5] {} } { 0.000ns 0.285ns 0.268ns 0.000ns } { 0.000ns 0.378ns 0.346ns 0.155ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[5] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst|count[5] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { c24:inst|count[5] {} } {  } {  } "" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pin_name pin_name1 c24:inst\|count\[3\] 6.041 ns register " "Info: tco from clock \"pin_name\" to destination pin \"pin_name1\" through register \"c24:inst\|count\[3\]\" is 6.041 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pin_name source 2.498 ns + Longest register " "Info: + Longest clock path from clock \"pin_name\" to source register is 2.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns pin_name 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'pin_name'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_name } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 240 408 224 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns pin_name~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'pin_name~clkctrl'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { pin_name pin_name~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 240 408 224 "pin_name" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.618 ns) 2.498 ns c24:inst\|count\[3\] 3 REG LCFF_X26_Y26_N27 4 " "Info: 3: + IC(0.683 ns) + CELL(0.618 ns) = 2.498 ns; Loc. = LCFF_X26_Y26_N27; Fanout = 4; REG Node = 'c24:inst\|count\[3\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.93 % ) " "Info: Total cell delay = 1.472 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 41.07 % ) " "Info: Total interconnect delay = 1.026 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.449 ns + Longest register pin " "Info: + Longest register to pin delay is 3.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c24:inst\|count\[3\] 1 REG LCFF_X26_Y26_N27 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y26_N27; Fanout = 4; REG Node = 'c24:inst\|count\[3\]'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { c24:inst|count[3] } "NODE_NAME" } } { "c24.vhd" "" { Text "F:/FPGA/1/c24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.357 ns) 0.877 ns pwm:inst1\|LessThan0~66 2 COMB LCCOMB_X26_Y26_N10 1 " "Info: 2: + IC(0.520 ns) + CELL(0.357 ns) = 0.877 ns; Loc. = LCCOMB_X26_Y26_N10; Fanout = 1; COMB Node = 'pwm:inst1\|LessThan0~66'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.877 ns" { c24:inst|count[3] pwm:inst1|LessThan0~66 } "NODE_NAME" } } { "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(2.046 ns) 3.449 ns pin_name1 3 PIN PIN_B9 0 " "Info: 3: + IC(0.526 ns) + CELL(2.046 ns) = 3.449 ns; Loc. = PIN_B9; Fanout = 0; PIN Node = 'pin_name1'" {  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.572 ns" { pwm:inst1|LessThan0~66 pin_name1 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/FPGA/1/Block1.bdf" { { 208 784 960 224 "pin_name1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.403 ns ( 69.67 % ) " "Info: Total cell delay = 2.403 ns ( 69.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 30.33 % ) " "Info: Total interconnect delay = 1.046 ns ( 30.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.449 ns" { c24:inst|count[3] pwm:inst1|LessThan0~66 pin_name1 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.449 ns" { c24:inst|count[3] {} pwm:inst1|LessThan0~66 {} pin_name1 {} } { 0.000ns 0.520ns 0.526ns } { 0.000ns 0.357ns 2.046ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.498 ns" { pin_name pin_name~clkctrl c24:inst|count[3] } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.498 ns" { pin_name {} pin_name~combout {} pin_name~clkctrl {} c24:inst|count[3] {} } { 0.000ns 0.000ns 0.343ns 0.683ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.449 ns" { c24:inst|count[3] pwm:inst1|LessThan0~66 pin_name1 } "NODE_NAME" } } { "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.449 ns" { c24:inst|count[3] {} pwm:inst1|LessThan0~66 {} pin_name1 {} } { 0.000ns 0.520ns 0.526ns } { 0.000ns 0.357ns 2.046ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 29 12:25:52 2008 " "Info: Processing ended: Tue Jul 29 12:25:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}