pwm3.vhd

来自「用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pwm3 is
port(dout:in std_logic_vector(7 downto 0);
	 pwm3:out std_logic);
end;
architecture one of pwm3 is
begin
process(dout)
begin
	if dout<12 then
		pwm3<='0';
	else pwm3<='1';	
end if;
end process;
end;