📄 c24.vhd
字号:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity c24 is
Port ( clk : in std_logic;
dout : out std_logic_vector(7 downto 0));
end c24;
architecture Behavioral of c24 is
signal count : std_logic_vector(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if count(3 downto 0)="1001" then
count(3 downto 0)<="0000";
count(5 downto 4)<=count(5 downto 4) +1;
else
count(3 downto 0)<=count(3 downto 0)+1;
end if;
if count="00100011" then
count<="00000000";
end if;
end if;
dout <= count;
end process;
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -