block1.tan.summary

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.866 ns
From           : c24:inst10|count[5]
To             : pwm5
From Clock     : clk5
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk5'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : c24:inst10|count[4]
To             : c24:inst10|count[5]
From Clock     : clk5
To Clock       : clk5
Failed Paths   : 0

Type           : Clock Setup: 'clk4'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : c24:inst9|count[1]
To             : c24:inst9|count[2]~DUPLICATE
From Clock     : clk4
To Clock       : clk4
Failed Paths   : 0

Type           : Clock Setup: 'clk3'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : c24:inst|count[4]
To             : c24:inst|count[2]~DUPLICATE
From Clock     : clk3
To Clock       : clk3
Failed Paths   : 0

Type           : Clock Setup: 'clk2'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : c24:inst8|count[3]
To             : c24:inst8|count[5]
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : c24:inst7|count[3]
To             : c24:inst7|count[2]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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