block1.tan.rpt

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y26_N23; Fanout = 5; REG Node = 'c24:inst8|count[3]'
            Info: 2: + IC(0.378 ns) + CELL(0.378 ns) = 0.756 ns; Loc. = LCCOMB_X17_Y26_N12; Fanout = 2; COMB Node = 'c24:inst8|Equal1~37'
            Info: 3: + IC(0.259 ns) + CELL(0.228 ns) = 1.243 ns; Loc. = LCCOMB_X17_Y26_N16; Fanout = 1; COMB Node = 'c24:inst8|count~267'
            Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.398 ns; Loc. = LCFF_X17_Y26_N17; Fanout = 4; REG Node = 'c24:inst8|count[5]'
            Info: Total cell delay = 0.761 ns ( 54.43 % )
            Info: Total interconnect delay = 0.637 ns ( 45.57 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk2" to destination register is 2.486 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 6; COMB Node = 'clk2~clkctrl'
                Info: 3: + IC(0.661 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X17_Y26_N17; Fanout = 4; REG Node = 'c24:inst8|count[5]'
                Info: Total cell delay = 1.482 ns ( 59.61 % )
                Info: Total interconnect delay = 1.004 ns ( 40.39 % )
            Info: - Longest clock path from clock "clk2" to source register is 2.486 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 6; COMB Node = 'clk2~clkctrl'
                Info: 3: + IC(0.661 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X17_Y26_N23; Fanout = 5; REG Node = 'c24:inst8|count[3]'
                Info: Total cell delay = 1.482 ns ( 59.61 % )
                Info: Total interconnect delay = 1.004 ns ( 40.39 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk3" Internal fmax is restricted to 500.0 MHz between source register "c24:inst|count[4]" and destination register "c24:inst|count[2]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.875 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y26_N21; Fanout = 5; REG Node = 'c24:inst|count[4]'
            Info: 2: + IC(0.363 ns) + CELL(0.357 ns) = 0.720 ns; Loc. = LCCOMB_X30_Y26_N0; Fanout = 1; COMB Node = 'c24:inst|count~265'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.875 ns; Loc. = LCFF_X30_Y26_N1; Fanout = 5; REG Node = 'c24:inst|count[2]'
            Info: Total cell delay = 0.512 ns ( 58.51 % )
            Info: Total interconnect delay = 0.363 ns ( 41.49 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk3" to destination register is 2.512 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 1; CLK Node = 'clk3'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G9; Fanout = 7; COMB Node = 'clk3~clkctrl'
                Info: 3: + IC(0.687 ns) + CELL(0.618 ns) = 2.512 ns; Loc. = LCFF_X30_Y26_N1; Fanout = 5; REG Node = 'c24:inst|count[2]'
                Info: Total cell delay = 1.482 ns ( 59.00 % )
                Info: Total interconnect delay = 1.030 ns ( 41.00 % )
            Info: - Longest clock path from clock "clk3" to source register is 2.512 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 1; CLK Node = 'clk3'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G9; Fanout = 7; COMB Node = 'clk3~clkctrl'
                Info: 3: + IC(0.687 ns) + CELL(0.618 ns) = 2.512 ns; Loc. = LCFF_X30_Y26_N21; Fanout = 5; REG Node = 'c24:inst|count[4]'
                Info: Total cell delay = 1.482 ns ( 59.00 % )
                Info: Total interconnect delay = 1.030 ns ( 41.00 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk4" Internal fmax is restricted to 500.0 MHz between source register "c24:inst9|count[1]" and destination register "c24:inst9|count[2]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.931 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y26_N13; Fanout = 6; REG Node = 'c24:inst9|count[1]'
            Info: 2: + IC(0.419 ns) + CELL(0.357 ns) = 0.776 ns; Loc. = LCCOMB_X14_Y26_N16; Fanout = 1; COMB Node = 'c24:inst9|count~272'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.931 ns; Loc. = LCFF_X14_Y26_N17; Fanout = 4; REG Node = 'c24:inst9|count[2]'
            Info: Total cell delay = 0.512 ns ( 54.99 % )
            Info: Total interconnect delay = 0.419 ns ( 45.01 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk4" to destination register is 2.485 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N3; Fanout = 1; CLK Node = 'clk4'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G11; Fanout = 7; COMB Node = 'clk4~clkctrl'
                Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X14_Y26_N17; Fanout = 4; REG Node = 'c24:inst9|count[2]'
                Info: Total cell delay = 1.472 ns ( 59.24 % )
                Info: Total interconnect delay = 1.013 ns ( 40.76 % )
            Info: - Longest clock path from clock "clk4" to source register is 2.485 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N3; Fanout = 1; CLK Node = 'clk4'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G11; Fanout = 7; COMB Node = 'clk4~clkctrl'
                Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X14_Y26_N13; Fanout = 6; REG Node = 'c24:inst9|count[1]'
                Info: Total cell delay = 1.472 ns ( 59.24 % )
                Info: Total interconnect delay = 1.013 ns ( 40.76 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk5" Internal fmax is restricted to 500.0 MHz between source register "c24:inst10|count[4]" and destination register "c24:inst10|count[5]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.827 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y1_N17; Fanout = 5; REG Node = 'c24:inst10|count[4]'
            Info: 2: + IC(0.294 ns) + CELL(0.378 ns) = 0.672 ns; Loc. = LCCOMB_X39_Y1_N2; Fanout = 1; COMB Node = 'c24:inst10|count~246'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.827 ns; Loc. = LCFF_X39_Y1_N3; Fanout = 4; REG Node = 'c24:inst10|count[5]'
            Info: Total cell delay = 0.533 ns ( 64.45 % )
            Info: Total interconnect delay = 0.294 ns ( 35.55 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk5" to destination register is 2.524 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N22; Fanout = 1; CLK Node = 'clk5'
                Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.218 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk5~clkctrl'
                Info: 3: + IC(0.688 ns) + CELL(0.618 ns) = 2.524 ns; Loc. = LCFF_X39_Y1_N3; Fanout = 4; REG Node = 'c24:inst10|count[5]'
                Info: Total cell delay = 1.482 ns ( 58.72 % )
                Info: Total interconnect delay = 1.042 ns ( 41.28 % )
            Info: - Longest clock path from clock "clk5" to source register is 2.524 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N22; Fanout = 1; CLK Node = 'clk5'
                Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.218 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk5~clkctrl'
                Info: 3: + IC(0.688 ns) + CELL(0.618 ns) = 2.524 ns; Loc. = LCFF_X39_Y1_N17; Fanout = 5; REG Node = 'c24:inst10|count[4]'
                Info: Total cell delay = 1.482 n